CRYPTOCELL triggers interrupt once processing is complete.
See register IRR for more information on which CRYPTOCELL subsystem components are able to trigger an interrupt request.
To clear the IRQ line when an interrupt has occurred, the relevant interrupt bit in register ICR must be cleared. Interrupt sources can be masked using register IMR. If an interrupt source is masked, no interrupt request will be triggered.
In addition if field RNG_INT in register IRR
is asserted, the relevant RNG engine interrupt bit in register RNG_ICR
must be cleared before clearing that interrupt bit in register
ICR as described above.
The figure below shows how the CRYPTOCELL subsystem interrupt handling is designed and how it is connected to the NVIC module in the CPU.