Registers

nRF5340 Product Specification

Instances

Instance Domain Base address TrustZone Split access Description
Map Att DMA

P0 : S
P0 : NS

 APPLICATION

0x50842500
0x40842500

 US S NA Yes

General purpose input and output, port 0

P1 : S
P1 : NS

 APPLICATION

0x50842800
0x40842800

 US S NA Yes

General purpose input and output, port 1
P0 NETWORK 0x418C0500 HF NS NA No

General purpose input and output
P1 NETWORK 0x418C0800 HF NS NA No

General purpose input and output

Configuration

Instance Domain Configuration

P0 : S
P0 : NS

 APPLICATION

P0.00 to P0.31 implemented

P1 : S
P1 : NS

 APPLICATION

P1.00 to P1.15 implemented
P0 NETWORK

P0.00 to P0.31 implemented
P1 NETWORK

P1.00 to P1.15 implemented

Register overview

Register Offset TZ Description
OUT 0x004

Write GPIO port

This register is retained.
OUTSET 0x008

Set individual bits in GPIO port
OUTCLR 0x00C

Clear individual bits in GPIO port
IN 0x010

Read GPIO port
DIR 0x014

Direction of GPIO pins

This register is retained.
DIRSET 0x018

DIR set register
DIRCLR 0x01C

DIR clear register
LATCH 0x020

Latch register indicating what GPIO pins that have met the criteria set in the PIN_CNF[n].SENSE registers

This register is retained.
DETECTMODE 0x024

Select between default DETECT signal behavior and LDETECT mode

This register is retained.
DETECTMODE_SEC 0x028

Select between default DETECT signal behavior and LDETECT mode

This register is retained.
PIN_CNF[n] 0x200

Configuration of GPIO pins

This register is retained.