PDMCLKCTRL

Address offset: 0x504

PDM clock generator control


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x08400000				0	0	0	0	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	FREQ										PDM_CLK frequency configuration. Enumerations are deprecated, use PDMCLKCTRL equation to find the register value. The 12 least significant bits of the register are ignored and shall be set to zero.
			1000K	0x08000000								PDM_CLK = 32 MHz / 32 = 1.000 MHz
			Default	0x08400000								PDM_CLK = 32 MHz / 31 = 1.032 MHz. Nominal clock for RATIO=Ratio64.
			1067K	0x08800000								PDM_CLK = 32 MHz / 30 = 1.067 MHz
			1231K	0x09800000								PDM_CLK = 32 MHz / 26 = 1.231 MHz
			1280K	0x0A000000								PDM_CLK = 32 MHz / 25 = 1.280 MHz. Nominal clock for RATIO=Ratio80.
			1333K	0x0A800000								PDM_CLK = 32 MHz / 24 = 1.333 MHz