DCNF protection blocks the path of AHB masters in an external core from accessing AHB
slaves in the AMLI of the local core. Essentially, blocking external core access to internal
resources of the local core.
The following figure is a simplified version of the AMLI that shows the set of
configuration registers used to control this behavior. A more detailed AMLI figure can be
found in Memory.
Figure 1. Domain configuration
The DCNF configuration registers that enable the DCNF protection are the following:
An attempt to access the blocked resources will trigger a BusFault or a HardFault exception,
depending on the value of the BUSFAULTENA bit in the Arm® Cortex®-M33 SHCSR
(system handler control and state register). This is described in the Arm Cortex-M33 Devices Generic User Guide.
RAM protection
RAM regions are protected by configuring the SLAVE bits in the register
EXTRAM[n].PROTECT of the equivalent master port.
Peripheral protection
Peripheral memory regions are protected by configuring the SLAVE bits in the register
EXTPERI[n].PROTECT of the equivalent master port.
Code protection
Code memory regions are protected by configuring the SLAVE bits in the register
EXTCODE[0].PROTECT of the equivalent master port.