Debug side registers

System reset request.

Perform a secure erase of the device, where flash, SRAM, and UICR will be erased in sequence. The device will be returned to factory default settings upon next reset.

This is the status register for the ERASEALL operation.

This register disables APPROTECT and enables debug access to non-secure mode.

This register disables SECUREAPPROTECT and enables debug access to secure mode.

This is the status register for the UICR ERASEPROTECT configuration.

This register disables ERASEPROTECT and performs ERASEALL.

Data sent from the debugger to the CPU.

This register shows a status that indicates if data sent from the debugger to the CPU has been read.

Data sent from the CPU to the debugger.

This register shows a status that indicates if data sent from the CPU to the debugger has been read.

CTRL-AP Identification Register, IDR.