The master clock source can be configured in register MCLKCONFIG. Choose one of the following as the master clock source:
- 32 MHz peripheral clock (PCLK32M), synchronous to HFCLK.
- Audio PLL clock (ACLK) with configurable frequency.
The peripheral must be stopped before selecting the master clock source. The use of the STOP task and the STOPPED event is described in Module operation.
To improve the master clock accuracy and jitter performance, it is recommended (but not mandatory) that the PCLK32M source is running off the HFXO instead of the HFINT oscillator. The ACLK source requires the use of HFXO. See CLOCK — Clock control for more information about starting HFXO for the relevant clock source.