The cache includes profiling counters IHIT, IMISS, DHIT, and DMISS for both flash and execute-in-place (XIP).
Cache performance on executed code is indicated by these counters when enabled through PROFILINGENABLE. The counters can be cleared at any time using PROFILINGCLEAR. Writing to this register will clear all profiling counters. After being cleared, the counters will increment at the next instruction, or data fetch, according to the rules in the following table.
| Profiling counter | Description |
|---|---|
| IHIT | Increased on a cache hit for instruction fetch |
| IMISS | Increased on a cache miss for instruction fetch |
| DHIT | Increased on a cache hit for data fetch (i.e. LOAD type instruction targeting the cache region) |
| DMISS | Increased on a cache miss for data fetch (i.e. LOAD type instruction targeting the cache region) |