CPULOCK

nRF5340 Product Specification

Address offset: 0x404

Configure bits to lock down CPU features at runtime

Write '1' to any position to set the corresponding lock bit, which will remain set until the next reset

Any '0' writes to this register will be ignored


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																															E	D	C	B	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW W1S	LOCKSVTAIRCR										Write '1' to prevent updating the secure interrupt configuration until the next reset When set to '1', this lock bit prevents changes to: The Secure vector table base address Handling of Secure interrupt priority BusFault, HardFault, and NMI security target
			Locked	1								Disables writes to the VTOR_S, AIRCR.PRIS, and AIRCR.BFHFNMINS registers
			Unlocked	0								These registers can be updated
B	RW W1S	LOCKNSVTOR										Write '1' to prevent updating the non-secure vector table base address until the next reset When set to '1', this lock bit prevents changes to the Non-secure interrupt vector table base address register VTOR_NS
			Locked	1								The address of the non-secure vector table is locked
			Unlocked	0								The address of the non-secure vector table can be updated
C	RW W1S	LOCKSMPU										Write '1' to prevent updating the secure MPU regions until the next reset When set to '1', this lock bit prevents changes to programmed Secure MPU memory regions and all writes to the registers are ignored
			Locked	1								Disables writes to the MPU_CTRL, MPU_RNR, MPU_RBAR, MPU_RLAR, MPU_RBAR_An and MPU_RLAR_An from software or from a debug agent connected to the processor in Secure state
			Unlocked	0								These registers can be updated
D	RW W1S	LOCKNSMPU										Write '1' to prevent updating the Non-secure MPU regions until the next reset When set to '1', this lock bit prevents changes to programmed Non-secure MPU memory regions already programmed. All writes to the registers are ignored.
			Locked	1								Disables writes to the MPU_CTRL_NS, MPU_RNR_NS, MPU_RBAR_NS, MPU_RLAR_NS, MPU_RBAR_A_NSn and MPU_RLAR_A_NSn from software or from a debug agent connected to the processor
			Unlocked	0								These registers can be updated
E	RW W1S	LOCKSAU										Write '1' to prevent updating the secure SAU regions until the next reset When set to '1', this lock bit prevents changes to Secure SAU memory regions already programmed. All writes to the registers are ignored.
			Locked	1								Disables writes to the SAU_CTRL, SAU_RNR, SAU_RBAR and SAU_RLAR registers from software or from a debug agent connected to the processor
			Unlocked	0								These registers can be updated