Enabling the trace port

nRF5340 Product Specification

A specific sequence of operations must be performed to enable the trace port.

  1. Enable the debug master. 
    NRF_TAD_S->ENABLE = TAD_ENABLE_ENABLE_Msk;
  2. Request clock startup. 
    NRF_TAD_S->CLOCKSTART = TAD_CLOCKSTART_START_Msk;
  3. Configure the trace port to use pins P0.08 through P0.12. 
    NRF_TAD_S->PSEL.TRACECLK   = TAD_PSEL_TRACECLK_PIN_Traceclk;
NRF_TAD_S->PSEL.TRACEDATA0 = TAD_PSEL_TRACEDATA0_PIN_Tracedata0;
NRF_TAD_S->PSEL.TRACEDATA1 = TAD_PSEL_TRACEDATA1_PIN_Tracedata1;
NRF_TAD_S->PSEL.TRACEDATA2 = TAD_PSEL_TRACEDATA2_PIN_Tracedata2;
NRF_TAD_S->PSEL.TRACEDATA3 = TAD_PSEL_TRACEDATA3_PIN_Tracedata3;
  4. Configure the GPIO pins so that the trace and debug system can control them. Set high drive strength to ensure sufficiently fast operation. Do this for all trace pins that should be used. 
    // Clear the bitfields before configuring to make sure the correct value is written
NRF_P0_S->PIN_CNF[TAD_PSEL_TRACECLK_PIN_Traceclk]
                    &= ~(GPIO_PIN_CNF_MCUSEL_Msk | GPIO_PIN_CNF_DRIVE_Msk);
NRF_P0_S->PIN_CNF[TAD_PSEL_TRACECLK_PIN_Traceclk]
                    |= (GPIO_PIN_CNF_MCUSEL_TND << GPIO_PIN_CNF_MCUSEL_Pos)
                     | (GPIO_PIN_CNF_DRIVE_E0E1 << GPIO_PIN_CNF_DRIVE_Pos);
  5. Set trace port speed to 64 MHz. 
    NRF_TAD_S->TRACEPORTSPEED = TAD_TRACEPORTSPEED_TRACEPORTSPEED_64MHz;
    Note: Although possible, it is not recommended to run the trace port at less than half the CPU frequency, as it risks dropping some trace packets.
  6. Configure Arm CoreSight components (see Arm CoreSight documentation for more information).