Two Wire Interface Master (TWIM) timing specifications

nRF5340 Product Specification

Symbol Description Min. Typ. Max. Units
tTWIM,SU_DATI

Input data setup time before positive edge on SCL – all modes

20 ns
tTWIM,HD_DATI

Input data hold time after negative edge on SCL – 100, 250 and 400 kbps

0 ns
tTWIM,HD_DATO

Output data hold time after negative edge on SCL – 100, 250 and 400 kbps

500 625 ns
tTWIM,HD_DATO,1000kbps

Output data hold time after negative edge on SCL – 1000 kbps

250 315 ns
tTWIM,HD_STA,100kbps

TWIM master hold time for START and repeated START condition, 100 kbps

9900 ns
tTWIM,HD_STA,250kbps

TWIM master hold time for START and repeated START condition, 250 kbps

3900 ns
tTWIM,HD_STA,400kbps

TWIM master hold time for START and repeated START condition, 400 kbps

2400 ns
tTWIM,HD_STA,1000kbps

TWIM master hold time for START and repeated START condition, 1000 kbps

900 ns
tTWIM,SU_STO,100kbps

TWIM master setup time from SCL high to STOP condition, 100 kbps

5000 ns
tTWIM,SU_STO,250kbps

TWIM master setup time from SCL high to STOP condition, 250 kbps

2000 ns
tTWIM,SU_STO,400kbps

TWIM master setup time from SCL high to STOP condition, 400 kbps

1250 ns
tTWIM,SU_STO,1000kbps

TWIM master setup time from SCL high to STOP condition, 1000 kbps

500 ns
tTWIM,BUF,100kbps

TWIM master bus free time between STOP and START conditions, 100 kbps

5250 ns
tTWIM,BUF,250kbps

TWIM master bus free time between STOP and START conditions, 250 kbps

2250 ns
tTWIM,BUF,400kbps

TWIM master bus free time between STOP and START conditions, 400 kbps

1500 ns
tTWIM,BUF,1000kbps

TWIM master bus free time between STOP and START conditions, 1000 kbps

750 ns
Figure 7. TWIM timing diagram, 1 byte transaction

TWIM timing diagram, 1 byte transaction