IRR

Address offset: 0xA00

Interrupt request register. Each bit of this register holds the interrupt status of a single interrupt source. If corresponding IMR bit is unmasked, an interrupt is generated.


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																								H	G	F	E	D	C	B	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	R	SRAM_TO_DIN_INT										The RNG SRAM to DIN DMA done interrupt status. This interrupt is asserted when all data was delivered from RNG SRAM to DIN buffer.
B	R	DOUT_TO_SRAM_INT										The DOUT to RNG SRAM DMA done interrupt status. This interrupt is asserted when all data was delivered from DOUT buffer to RNG SRAM.
C	R	MEM_TO_DIN_INT										The memory to DIN DMA done interrupt status. This interrupt is asserted when all data was delivered from memory to DIN buffer.
D	R	DOUT_TO_MEM_INT										The DOUT to memory DMA done interrupt status. This interrupt is asserted when all data was delivered from DOUT buffer to memory.
E	R	AHB_ERR_INT										The AHB error interrupt status.
F	R	PKA_INT										The PKA end of operation interrupt status.
G	R	RNG_INT										The RNG interrupt status.
H	R	SYM_DMA_INT										The symmetric engine DMA completed interrupt status.