An instruction cache (I-Cache) can be enabled for the ICODE bus in the NVMC.
See Memory for the location of flash.
A cache hit is an instruction fetch from the cache, and it has a 0 wait-state
delay. The number of wait-states for a cache miss, where the instruction is not available in the
cache and needs to be fetched from flash, depends on the processor frequency, see CPU parameter
W_FLASHCACHE.
Enabling the cache can increase the CPU performance, and reduce power consumption by reducing the number of wait cycles and the number of flash accesses. This will depend on the cache hit rate. Cache draws current when enabled. If the reduction in average current due to reduced flash accesses is larger than the cache power requirement, the average current to execute the program code will be reduced.
When disabled, the cache does not draw current and its content is not retained.
It is possible to enable cache profiling to analyze the performance of the cache for your program using the register ICACHECNF. When profiling is enabled, registers IHIT and IMISS are incremented for every instruction cache hit or miss respectively.