CLK_STATUS

Address offset: 0x824

CRYPTOCELL clocks status register.


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																											E	D				C	B		A
Reset 0x00000100				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	R	AES_CLK										Status of AES engine clock.
			Disabled	0								Clock for AES engine is disabled
			Enabled	1								Clock for AES engine is enabled
B	R	HASH_CLK										Status of HASH engine clock.
			Disabled	0								Clock for HASH engine is disabled
			Enabled	1								Clock for HASH engine is enabled
C	R	PKA_CLK										Status of PKA engine clock.
			Disabled	0								Clock for PKA engine is disabled
			Enabled	1								Clock for PKA engine is enabled
D	R	CHACHA_CLK										Status of CHACHA engine clock.
			Disabled	0								Clock for CHACHA engine is disabled
			Enabled	1								Clock for CHACHA engine is enabled
E	R	DMA_CLK										Status of DMA engines clock.
			Disabled	0								Clocks for DMA engines are disabled
			Enabled	1								Clocks for DMA engines are enabled