The UARTE receiver is started by triggering the STARTRX task. The UARTE receiver uses EasyDMA to store incoming data in an RX buffer in RAM.
The RX buffer is located at the address specified in the RXD.PTR register. The RXD.PTR register is double-buffered and it can be updated and prepared for the next STARTRX task immediately after the RXSTARTED event is generated. The size of the RX buffer is specified in the RXD.MAXCNT register. UARTE generates an ENDRX event when it has filled up the RX buffer, as seen in the following figure.
For each byte received over the RXD line, an RXDRDY event is generated. This event is likely to occur before the corresponding data has been transferred to Data RAM.
The RXD.AMOUNT register can be queried following an ENDRX event to see how many new bytes have been transferred to the RX buffer in RAM since the previous ENDRX event.
The UARTE receiver is stopped by triggering the STOPRX task. An RXTO event is generated when the UARTE has stopped. UARTE makes sure that an impending ENDRX event is generated before the RXTO event is generated. This means that UARTE guarantees that no ENDRX event is generated after RXTO, unless UARTE is restarted or a FLUSHRX command is issued after the RXTO event is generated.
To determine the amount of bytes the RX buffer has received, the CPU can read the RXD.AMOUNT register following the ENDRX event or the RXTO event.
UARTE can receive up to four bytes after the STOPRX task has been triggered, if these are sent in succession immediately after the RTS signal is deactivated.
After the RXTO event is generated, the internal RX FIFO may still contain data. To move this data to RAM, the FLUSHRX task must be triggered. The RX buffer should be emptied, or the RXD.PTR register should be updated before the FLUSHRX task is triggered. This ensures the data in the RX buffer is not overwritten. To make sure that all data in the RX FIFO is moved to the RX buffer, the RXD.MAXCNT register must be set to RXD.MAXCNT > 4, as seen in the following figure. The UARTE will generate the ENDRX event after completing the FLUSHRX task even if the RX FIFO was empty or if the RX buffer does not fill up. After the ENDRX event, the RXD.AMOUNT register holds the actual amount of bytes transferred to the RX buffer.
If hardware flow control is enabled through the HWFC field in the CONFIG register, the RTS signal will be deactivated when the receiver is stopped via the STOPRX task or when the UARTE is only able to receive four more bytes in its internal RX FIFO.
With flow control disabled, the UARTE will function in the same way as when the flow control is enabled except that the RTS line will not be used. This means that no signal will be generated when the UARTE has reached the point where it is only able to receive four more bytes in its internal RX FIFO. Data received when the internal RX FIFO is filled up, will be lost.
The UARTE receiver will be in its lowest activity level, and consume the least amount of energy, when it is stopped, i.e. before it is started via STARTRX or after it has been stopped via STOPRX and the RXTO event has been generated. See POWER — Power control for more information about power modes.