Registers

nRF5340 Product Specification

Instances

Instance Domain Base address TrustZone Split access Description
Map Att DMA

SPIM0 : S
SPIM0 : NS

APPLICATION

0x50008000
0x40008000

US S SA No

SPI master 0

SPIM1 : S
SPIM1 : NS

APPLICATION

0x50009000
0x40009000

US S SA No

SPI master 1

SPIM4 : S
SPIM4 : NS

APPLICATION

0x5000A000
0x4000A000

US S SA No

SPI master 4 (high-speed)

SPIM2 : S
SPIM2 : NS

APPLICATION

0x5000B000
0x4000B000

US S SA No

SPI master 2

SPIM3 : S
SPIM3 : NS

APPLICATION

0x5000C000
0x4000C000

US S SA No

SPI master 3

SPIM0 NETWORK 0x41013000 HF NS NA No

SPI master 0

Configuration

Instance Domain Configuration

SPIM0 : S
SPIM0 : NS

APPLICATION

Not supported: > 8 Mbps data rate, CSNPOL register, DCX functionality, IFTIMING.x registers, hardware CSN control (PSEL.CSN), stalling mechanism during AHB bus contention

SPIM1 : S
SPIM1 : NS

APPLICATION

Not supported: > 8 Mbps data rate, CSNPOL register, DCX functionality, IFTIMING.x registers, hardware CSN control (PSEL.CSN), stalling mechanism during AHB bus contention

SPIM4 : S
SPIM4 : NS

APPLICATION

Up to 32 Mbps SPI when using dedicated pins

SPIM2 : S
SPIM2 : NS

APPLICATION

Not supported: > 8 Mbps data rate, CSNPOL register, DCX functionality, IFTIMING.x registers, hardware CSN control (PSEL.CSN), stalling mechanism during AHB bus contention

SPIM3 : S
SPIM3 : NS

APPLICATION

Not supported: > 8 Mbps data rate, CSNPOL register, DCX functionality, IFTIMING.x registers, hardware CSN control (PSEL.CSN), stalling mechanism during AHB bus contention

SPIM0 NETWORK

Not supported: > 8 Mbps data rate, IFTIMING.x registers, hardware CSN control (PSEL.CSN), stalling mechanism during AHB bus contention

Register overview

Register Offset TZ Description
TASKS_START 0x010

Start SPI transaction

TASKS_STOP 0x014

Stop SPI transaction

TASKS_SUSPEND 0x01C

Suspend SPI transaction

TASKS_RESUME 0x020

Resume SPI transaction

SUBSCRIBE_START 0x090

Subscribe configuration for task START

SUBSCRIBE_STOP 0x094

Subscribe configuration for task STOP

SUBSCRIBE_SUSPEND 0x09C

Subscribe configuration for task SUSPEND

SUBSCRIBE_RESUME 0x0A0

Subscribe configuration for task RESUME

EVENTS_STOPPED 0x104

SPI transaction has stopped

EVENTS_ENDRX 0x110

End of RXD buffer reached

EVENTS_END 0x118

End of RXD buffer and TXD buffer reached

EVENTS_ENDTX 0x120

End of TXD buffer reached

EVENTS_STARTED 0x14C

Transaction started

PUBLISH_STOPPED 0x184

Publish configuration for event STOPPED

PUBLISH_ENDRX 0x190

Publish configuration for event ENDRX

PUBLISH_END 0x198

Publish configuration for event END

PUBLISH_ENDTX 0x1A0

Publish configuration for event ENDTX

PUBLISH_STARTED 0x1CC

Publish configuration for event STARTED

SHORTS 0x200

Shortcuts between local events and tasks

INTENSET 0x304

Enable interrupt

INTENCLR 0x308

Disable interrupt

STALLSTAT 0x400

Stall status for EasyDMA RAM accesses. The fields in this register are set to STALL by hardware whenever a stall occurres and can be cleared (set to NOSTALL) by the CPU.

ENABLE 0x500

Enable SPIM

PSEL.SCK 0x508

Pin select for SCK

PSEL.MOSI 0x50C

Pin select for MOSI signal

PSEL.MISO 0x510

Pin select for MISO signal

PSEL.CSN 0x514

Pin select for CSN

FREQUENCY 0x524

SPI frequency. Accuracy depends on the HFCLK source selected.

RXD.PTR 0x534

Data pointer

RXD.MAXCNT 0x538

Maximum number of bytes in receive buffer

RXD.AMOUNT 0x53C

Number of bytes transferred in the last transaction

RXD.LIST 0x540

EasyDMA list type

TXD.PTR 0x544

Data pointer

TXD.MAXCNT 0x548

Number of bytes in transmit buffer

TXD.AMOUNT 0x54C

Number of bytes transferred in the last transaction

TXD.LIST 0x550

EasyDMA list type

CONFIG 0x554

Configuration register

IFTIMING.RXDELAY 0x560

Sample delay for input serial data on MISO

IFTIMING.CSNDUR 0x564

Minimum duration between edge of CSN and edge of SCK. When SHORTS.END_START is used, this is also the minimum duration CSN must stay high between transactions.

CSNPOL 0x568

Polarity of CSN output

PSELDCX 0x56C

Pin select for DCX signal

DCXCNT 0x570

DCX configuration

ORC 0x5C0

Byte transmitted after TXD.MAXCNT bytes have been transmitted in the case when RXD.MAXCNT is greater than TXD.MAXCNT