SPU and the logic it controls will respond with a certain behavior once an access violation is detected.
The following actions will happen once the logic controlled by the SPU detects an access violation on one of the RAM ports:
- The faulty transfer will be blocked.
- In case of a read transfer, the bus will be driven to zero.
- If supported by the master, feedback will be sent to the master through specific bus error signals.
- A SecureFault exception will be triggered if security violation is detected for access from Arm Cortex-M33
- A BusFault exception will be triggered when read/write/execute protection violation is detected for Arm Cortex-M33. The SPU will also generate an event that can optionally trigger an interrupt towards the CPU.
- The RAMACCERR event will be triggered if any access violations are detected for all master types but for Arm Cortex-M33 security violation
The following table summarizes the SPU behavior based on the type of initiator and access violation.
| Master type | Security violation | Read/Write/Execute protection violation |
|---|---|---|
| Arm Cortex-M33 | SecureFault exception | BusFault exception, RAMACCERR event |
| EasyDMA | RAZ/WI, RAMACCERR event | RAZ/WI, RAMACCERR event |
| Other masters | RAZ/WI, RAMACCERR event | RAZ/WI, RAMACCERR event |
For the Arm Cortex-M33 master, the SecureFault exception will take precedence over the BusFault exception if a security violation occurs simultaneously with another type of violation.