Application core reset behavior

Application core reset behavior depends on the reset source.

Any reset in the application core will cause a network core Force-OFF, triggering the FORCEOFF reset source in the network core. For more information, see Network Force-OFF.

In System OFF mode, the watchdog timer is not running and there is no CPU lockup possible. RAM may be fully or partially retained, depending on RAM retention settings in VMC — Volatile memory controller.

If the device is in Debug Interface mode, the debug components will not be reset. Additionally, CPU lockup will not generate a reset. See Debug and trace for more information about the different debug components in the system.

Application core reset targets and their reset sources are summarized in the following table.

Table 1. Application core reset targets and their reset sourcesAn 'x' in the table means that the specific module is reset.
Reset source	Reset target
Reset source	CPU	Network core	Debug	RAM	WDT	RESETREAS
CPU lockup	x	x
Soft reset	x	x
Wakeup from System OFF mode reset	x	x	x	x^¹	x
Watchdog timer reset	x	x	x	x	x
Pin reset	x	x	x	x	x
Brownout reset	x	x	x	x	x	x
Power-on reset	x	x	x	x	x	x
NETWORK.FORCEOFF		x

Note: RAM is never reset, but depending on the reset source, its content may be corrupted.

Some retained registers may have a different reset behavior, as shown in the following table.

Table 2. Application core reset behavior for retained registersAn 'x' in the table means that the specific module is reset.
Reset source	Reset target
Reset source	Regular peripheral registers	SPU	GPIO	REGULATORS, OSCILLATORS	POWERGPREGRET
CPU lockup	x	x	x^²
Soft reset	x	x	x^²
Wakeup from System OFF mode reset	x
Watchdog timer reset	x	x	x	x
Pin reset	x	x	x	x
Brownout reset	x	x	x	x	x
Power-on reset	x	x	x	x	x

¹ Depending on RAM retention settings.

² Except MCUSEL field, the MCUSEL register of the GPIO peripheral is not reset for CPU lockup and Soft reset.