Registers

CRYPTOCELL HOST register interface

Interrupt request register. Each bit of this register holds the interrupt status of a single interrupt source. If corresponding IMR bit is unmasked, an interrupt is generated.

Interrupt mask register. Each bit of this register holds the mask of a single interrupt source.

Interrupt clear register. Writing a 1 bit into a field in this register will clear the corresponding bit in IRR.

This register defines the endianness of the Host-accessible registers, and can only be written once.

This register holds the CRYPTOCELL subsystem signature. See reset value.

Hardware configuration of the CRYPTOCELL subsystem. Reset value holds the supported features.

Idle state register for the CRYPTOCELL subsystem.

This register start the power-down sequence.