Instances
| Instance | Domain | Base address | TrustZone | Split access | Description | ||
|---|---|---|---|---|---|---|---|
| Map | Att | DMA | |||||
|
QSPI : S |
APPLICATION |
0x5002B000 |
US | S | SA | No |
External memory (quad serial peripheral) interface |
Configuration
| Instance | Domain | Configuration |
|---|---|---|
|
QSPI : S |
APPLICATION |
Supports 192 MHz and 96 MHz PCLK192M frequency |
Register overview
| Register | Offset | TZ | Description |
|---|---|---|---|
| TASKS_ACTIVATE | 0x000 |
Activate QSPI interface |
|
| TASKS_READSTART | 0x004 |
Start transfer from external flash memory to internal RAM |
|
| TASKS_WRITESTART | 0x008 |
Start transfer from internal RAM to external flash memory |
|
| TASKS_ERASESTART | 0x00C |
Start external flash memory erase operation |
|
| TASKS_DEACTIVATE | 0x010 |
Deactivate QSPI interface |
|
| SUBSCRIBE_ACTIVATE | 0x080 |
Subscribe configuration for task ACTIVATE |
|
| SUBSCRIBE_READSTART | 0x084 |
Subscribe configuration for task READSTART |
|
| SUBSCRIBE_WRITESTART | 0x088 |
Subscribe configuration for task WRITESTART |
|
| SUBSCRIBE_ERASESTART | 0x08C |
Subscribe configuration for task ERASESTART |
|
| SUBSCRIBE_DEACTIVATE | 0x090 |
Subscribe configuration for task DEACTIVATE |
|
| EVENTS_READY | 0x100 |
QSPI peripheral is ready. This event will be generated as a response to all QSPI tasks except DEACTIVATE. |
|
| PUBLISH_READY | 0x180 |
Publish configuration for event READY |
|
| INTEN | 0x300 |
Enable or disable interrupt |
|
| INTENSET | 0x304 |
Enable interrupt |
|
| INTENCLR | 0x308 |
Disable interrupt |
|
| ENABLE | 0x500 |
Enable QSPI peripheral and acquire the pins selected in PSELn registers |
|
| READ.SRC | 0x504 |
Flash memory source address |
|
| READ.DST | 0x508 |
RAM destination address |
|
| READ.CNT | 0x50C |
Read transfer length |
|
| WRITE.DST | 0x510 |
Flash destination address |
|
| WRITE.SRC | 0x514 |
RAM source address |
|
| WRITE.CNT | 0x518 |
Write transfer length |
|
| ERASE.PTR | 0x51C |
Start address of flash block to be erased |
|
| ERASE.LEN | 0x520 |
Size of block to be erased. |
|
| PSEL.SCK | 0x524 |
Pin select for serial clock SCK |
|
| PSEL.CSN | 0x528 |
Pin select for chip select signal CSN. |
|
| PSEL.IO0 | 0x530 |
Pin select for serial data MOSI/IO0. |
|
| PSEL.IO1 | 0x534 |
Pin select for serial data MISO/IO1. |
|
| PSEL.IO2 | 0x538 |
Pin select for serial data WP/IO2. |
|
| PSEL.IO3 | 0x53C |
Pin select for serial data HOLD/IO3. |
|
| XIPOFFSET | 0x540 |
Address offset into the external memory for Execute in Place operation. |
|
| IFCONFIG0 | 0x544 |
Interface configuration. |
|
| XIPEN | 0x54C |
Enable Execute in Place operation. |
|
| XIP_ENC.KEY0 | 0x560 |
Bits 31:0 of XIP AES KEY |
|
| XIP_ENC.KEY1 | 0x564 |
Bits 63:32 of XIP AES KEY |
|
| XIP_ENC.KEY2 | 0x568 |
Bits 95:64 of XIP AES KEY |
|
| XIP_ENC.KEY3 | 0x56C |
Bits 127:96 of XIP AES KEY |
|
| XIP_ENC.NONCE0 | 0x570 |
Bits 31:0 of XIP NONCE |
|
| XIP_ENC.NONCE1 | 0x574 |
Bits 63:32 of XIP NONCE |
|
| XIP_ENC.NONCE2 | 0x578 |
Bits 95:64 of XIP NONCE |
|
| XIP_ENC.ENABLE | 0x57C |
Enable stream cipher for XIP |
|
| DMA_ENC.KEY0 | 0x580 |
Bits 31:0 of DMA AES KEY |
|
| DMA_ENC.KEY1 | 0x584 |
Bits 63:32 of DMA AES KEY |
|
| DMA_ENC.KEY2 | 0x588 |
Bits 95:64 of DMA AES KEY |
|
| DMA_ENC.KEY3 | 0x58C |
Bits 127:96 of DMA AES KEY |
|
| DMA_ENC.NONCE0 | 0x590 |
Bits 31:0 of DMA NONCE |
|
| DMA_ENC.NONCE1 | 0x594 |
Bits 63:32 of DMA NONCE |
|
| DMA_ENC.NONCE2 | 0x598 |
Bits 95:64 of DMA NONCE |
|
| DMA_ENC.ENABLE | 0x59C |
Enable stream cipher for EasyDMA |
|
| IFCONFIG1 | 0x600 |
Interface configuration. |
|
| STATUS | 0x604 |
Status register. |
|
| DPMDUR | 0x614 |
Set the duration required to enter/exit deep power-down mode (DPM). |
|
| ADDRCONF | 0x624 |
Extended address configuration. |
|
| CINSTRCONF | 0x634 |
Custom instruction configuration register. |
|
| CINSTRDAT0 | 0x638 |
Custom instruction data register 0. |
|
| CINSTRDAT1 | 0x63C |
Custom instruction data register 1. |
|
| IFTIMING | 0x640 |
SPI interface timing. |