Cryptographic flow

    
    uint8_t buf_src[32] =  {
          0xFA,0xFA,0xFA,0xFA,0xFA,0xFA,0xFA,0xFA,
          0xFA,0xFA,0xFA,0xFA,0xFA,0xFA,0xFA,0xFA,
          0xFA,0xFA,0xFA,0xFA,0xFA,0xFA,0xFA,0xFA,
          0xFA,0xFA,0xFA,0xFA,0xFA,0xFA,0xFA,0xFA };

    /* Enable CRYPTOCELL subsystem */
    NRF_CRYPTOCELL->ENABLE = CRYPTOCELL_ENABLE_ENABLE_Enabled;

    /* Enable engine and DMA clock */
    NRF_CC_MISC->HASH_CLK = CC_MISC_HASH_CLK_ENABLE_Enable;
    NRF_CC_MISC->DMA_CLK = CC_MISC_DMA_CLK_ENABLE_Enable;

    /* Wait until hash engine is Idle  */
    while (NRF_CC_CTL->HASH_BUSY == CC_CTL_HASH_BUSY_STATUS_Busy) {}

    /* Clear all interrupts */
    NRF_CC_HOST_RGF->ICR = 0xFFFFFFFF;

    /* Configure HASH as cryptographic flow */
    NRF_CC_CTL->CRYPTO_CTL = CC_CTL_CRYPTO_CTL_MODE_HashActive;

    /* Configure engine for SHA256 */
    NRF_CC_HASH->HASH_CONTROL = CC_HASH_HASH_CONTROL_MODE_SHA256;
    
    /* Enable automatic HW padding */
    NRF_CC_HASH->HASH_PAD = CC_HASH_HASH_PAD_ENABLE_Enable;
    NRF_CC_HASH->HASH_PAD_AUTO = CC_HASH_HASH_PAD_AUTO_HWPAD_Enable;

    /* Configure initial SHA256 values */
    NRF_CC_HASH->HASH_H[7] = 0x5BE0CD19;
    NRF_CC_HASH->HASH_H[6] = 0x1F83D9AB;
    NRF_CC_HASH->HASH_H[5] = 0x9B05688C;
    NRF_CC_HASH->HASH_H[4] = 0x510E527F;
    NRF_CC_HASH->HASH_H[3] = 0xA54FF53A;
    NRF_CC_HASH->HASH_H[2] = 0x3C6EF372;
    NRF_CC_HASH->HASH_H[1] = 0xBB67AE85;
    NRF_CC_HASH->HASH_H[0] = 0x6A09E667;

    /* Configure DMA input source address to start the cryptographic operation */
    NRF_CC_DIN->SRC_MEM_ADDR = (uint32_t) buf_src;
    NRF_CC_DIN->SRC_MEM_SIZE = (uint32_t) sizeof(buf_src);

    /* Wait on DIN DMA interrupt indicating data has been fetched */
    while(!(NRF_CC_HOST_RGF->IRR & CC_HOST_RGF_IRR_MEM_TO_DIN_INT_Msk)) {}

    /* Wait until hash engine is Idle */
    while (NRF_CC_CTL->HASH_BUSY == CC_CTL_HASH_BUSY_STATUS_Busy) {}

    /* Calculated SHA256 digest now available in 
    NRF_CC_HASH->HASH_H[0] to NRF_CC_HASH->HASH_H[7]  */