Configuration examples

Configuration examples for CLKCONFIG = PCLK32M and Configuration examples for CLKCONFIG = ACLK show some configuration examples for popular sample rates, using both the 32 MHz master clock and the Audio PLL clock source.

Table 2. Configuration examples for CLKCONFIG = PCLK32M

Source frequency [Hz]	Requested LRCK [Hz]	RATIO	Requested MCK [Hz]	MCKFREQ	MCK [Hz]	LRCK [Hz]	LRCK error [%]
32000000	16000	32	512000	68173824	507936	15873	-0.8
32000000	16000	64	1024000	135274496	1032258	16129	0.8
32000000	16000	256	4096000	516685824	4000000	15625	-2.3
32000000	32000	32	1024000	135274496	1032258	32258	0.8
32000000	32000	64	2048000	266350592	2000000	31250	-2.3
32000000	32000	256	8192000	974741504	8000000	31250	-2.3
32000000	44100	32	1411200	185319424	1391304	43478	-1.4
32000000	44100	64	2822400	362815488	2909090	45455	3.1
32000000	48000	32	1536000	201326592	1523809	47619	-0.8
32000000	48000	64	3072000	393428992	3200000	50000	4.2
32000000	96000	32	3072000	393428992	3200000	100000	4.2
32000000	96000	64	6144000	752402432	6400000	100000	4.2

Table 3. Configuration examples for CLKCONFIG = ACLK

Source frequency [Hz]	Requested LRCK [Hz]	RATIO	Requested MCK [Hz]	MCKFREQ	MCK [Hz]	LRCK [Hz]	LRCK error [%]
11289600	44100	32	1411200	505286656	1411200	44100	0
11289600	44100	64	2822400	954433536	2822400	44100	0
12288000	16000	32	510000	175304704	512000	16000	0
12288000	16000	64	1024000	343597056	1024000	16000	0
12288000	32000	32	1024000	343597056	1024000	32000	0
12288000	32000	64	2048000	660762624	2048000	32000	0
12288000	48000	32	1536000	505286656	1536000	48000	0
12288000	48000	64	3072000	954433536	3072000	48000	0
12288000	96000	32	3072000	954433536	3072000	96000	0