Registers

AES key value to use in non-tunneling operations, or as the first tunnel stage key in tunneling operations. The initial AES_KEY_0[0] register holds the least significant bits [31:0] of the key value.

AES key value to use as the second tunnel stage key in tunneling operations. The initial AES_KEY_1[0] register holds the least significant bits [31:0] of the key value.

AES Initialization Vector (IV) to use in non-tunneling operations, or as the first tunnel stage IV in tunneling operations. The initial AES_IV_0[0] register holds the least significant bits [31:0] of the IV.

AES Initialization Vector (IV) to use as the second tunnel stage IV in tunneling operations. The initial AES_IV_1[0] register holds the least significant bits [31:0] of the IV.

AES counter (CTR) to use in non-tunneling and tunneling operations. The initial AES_CTR[0] register holds the least significant bits [31:0] of the CTR.

Status register for AES engine activity.

Writing to this address triggers the AES engine to generate K1 and K2 for AES-CMAC operations.

This register should be set with the amount of remaining bytes until the end of the current AES operation.

Control the AES engine behavior.

Hardware configuration of the AES engine. Reset value holds the supported features.

This register enables the AES CTR no increment mode in which the counter mode is not incremented between two blocks

Reset the AES engine.

Writing to this address triggers the AES engine to perform a CMAC operation with size 0. The CMAC result can be read from the AES_IV_0 register.