The SCK, CSN, DCX, MOSI, and MISO signals associated with the SPIM are mapped to physical pins according to the configuration specified in the PSEL.n registers.
The contents of registers PSEL.SCK, PSEL.CSN, PSELDCX, PSEL.MOSI, and PSEL.MISO are only used when the SPIM is enabled and retained only as long as the device is in System ON mode. The PSEL.n registers can only be configured when the SPIM is disabled. Enabling/disabling is done using register ENABLE.
To ensure correct behavior, the pins used by the SPIM must be configured in the GPIO peripheral as described in GPIO configuration before the SPIM is enabled. Make sure to activate the dedicated peripheral setting of the GPIO pin. See GPIO — General purpose input/output for details on how to assign pins between cores, peripherals, or subsystems. For pin recommendations, see Pin assignments.
Only one peripheral can be assigned to drive a particular GPIO pin at a time. Failing to do so may result in unpredictable behavior.
| SPI master signal | SPI master pin | Direction | Output value |
|---|---|---|---|
| SCK | As specified in PSEL.SCK | Output | Same as CONFIG.CPOL |
| CSN | As specified in PSEL.CSN | Output | Same as CONFIG.CPOL |
| DCX | As specified in PSELDCX | Output | 1 |
| MOSI | As specified in PSEL.MOSI | Output | 0 |
| MISO | As specified in PSEL.MISO | Input | Not applicable |
Some SPIM instances do not support automatic control of CSN, and for those the available GPIO pins need to be used to control CSN directly. See Instances for information about what features are supported in the various SPIM instances.
The SPIM supports SPI modes 0 through 3. The clock polarity (CPOL) and the clock phase (CPHA) are configured in register CONFIG.
| Mode | Clock polarity | Clock phase |
|---|---|---|
| CPOL | CPHA | |
| SPI_MODE0 | 0 (Active High) | 0 (Leading) |
| SPI_MODE1 | 0 (Active High) | 1 (Trailing) |
| SPI_MODE2 | 1 (Active Low) | 0 (Leading) |
| SPI_MODE3 | 1 (Active Low) | 1 (Trailing) |