The clock source for the master clock generator can be selected in the register CONFIG.CLKCONFIG. Choose one of the following clocks as the clock source:
- 32 MHz peripheral clock (PCLK32M), synchronous to HFCLK.
- Audio PLL clock (ACLK) with configurable frequency.
To improve the master clock accuracy and jitter performance, it is recommended (but not mandatory) that the PCLK32M source is running off the HFXO instead of the HFINT oscillator. The ACLK source requires the use of HFXO. See CLOCK — Clock control for more information about starting HFXO for the relevant clock source.
The master clock generator can be bypassed so the MCK clock is derived directly from the input source. This can be configured in the BYPASS field of register CONFIG.CLKCONFIG.