SPU and the logic controlled by it will respond with a certain behavior once an access violation is detected.
The following actions will happen once the logic controlled by SPU detects an access violation on one of the flash ports:
- The faulty transfer will be blocked.
- In case of a read transfer, the bus will be driven to zero.
- If supported by the master, feedback will be sent to the master through specific bus error signals. At the same time, SPU will receive an event that can optionally trigger a CPU interrupt.
- A SecureFault exception will be triggered if a security violation is detected for access from the CPU.
- A BusFault exception will be triggered when a read/write/execute protection violation is detected from the CPU.
- The FLASHACCERR event will be triggered if any access violations are detected for all master types except for the CPU security violation.
The following table summarizes the SPU behavior based on the type of initiator and access violation.
| Master type | Security violation | Read/Write/Execute protection violation |
|---|---|---|
| Arm Cortex-M33 | SecureFault exception | BusFault exception, FLASHACCERR event |
| EasyDMA | RAZ/WI, FLASHACCERR event | RAZ/WI, FLASHACCERR event |
| Other masters | RAZ/WI, FLASHACCERR event | RAZ/WI, FLASHACCERR event |
For the Arm Cortex-M33 master, the SecureFault exception will take precedence over the BusFault exception if a security violation occurs simultaneously with another type of violation.