Instances
| Instance | Domain | Base address | TrustZone | Split access | Description | ||
|---|---|---|---|---|---|---|---|
| Map | Att | DMA | |||||
|
FPU : S |
APPLICATION |
0x50000000 |
US | S | NA | No |
Floating Point unit interrupt control |
Register overview
| Register | Offset | TZ | Description |
|---|---|---|---|
| EVENTS_INVALIDOPERATION | 0x100 |
An FPUIOC exception triggered by an invalid operation has occurred in the FPU |
|
| EVENTS_DIVIDEBYZERO | 0x104 |
An FPUDZC exception triggered by a floating-point divide-by-zero operation has occurred in the FPU |
|
| EVENTS_OVERFLOW | 0x108 |
An FPUOFC exception triggered by a floating-point overflow has occurred in the FPU |
|
| EVENTS_UNDERFLOW | 0x10C |
An FPUUFC exception triggered by a floating-point underflow has occurred in the FPU |
|
| EVENTS_INEXACT | 0x110 |
An FPUIXC exception triggered by an inexact floating-point operation has occurred in the FPU |
|
| EVENTS_DENORMALINPUT | 0x114 |
An FPUIDC exception triggered by a denormal floating-point input has occurred in the FPU |
|
| INTEN | 0x300 |
Enable or disable interrupt |
|
| INTENSET | 0x304 |
Enable interrupt |
|
| INTENCLR | 0x308 |
Disable interrupt |