Registers

Cryptographic results directly accessible by the CPU.

Status register for DOUT DMA engine activity when accessing memory.

Data destination address in memory.

The number of bytes to be written to memory.

Data destination address in RNG SRAM.

The number of bytes to be written to RNG SRAM.

Status register for DOUT DMA engine activity when accessing RNG SRAM.

Configure the endianness of DOUT DMA transactions towards RNG SRAM.

Indication that the next CPU read from the DOUT_BUFFER is the last in the sequence. This is needed only when the data size is NOT modulo 4 (e.g. HASH padding).

Register indicating if DOUT FIFO is empty or if more data will come.

Reset the DOUT DMA engine.