Electrical specification

nRF5340 Product Specification

nRF5340 Product Specification
Revision history
About this document
Document status
Peripheral chapters
Peripheral instantiation
Register overview table
Register tables
Fields and values
Permissions
Registers
DUMMY
Product overview
Block diagram
Memory
RAM — Random access memory
Flash — Non-volatile memory
XIP — Execute in place
Access latency
Power and clock management
System ON mode
Power submodes
System OFF mode
Emulated System OFF mode
Force-OFF mode
Emulated Force-OFF mode
Current consumption
Electrical specification
Sleep
Application CPU running
Network CPU running
COMP active
I2S active
LPCOMP active
NFCT active
PDM active
PWM active
QDEC active
QSPI active
RADIO transmitting/receiving
RNG active
SAADC active
TEMP active
TIMER running
SPIM active
SPIS active
TWIM active
TWIS active
UARTE active
WDT active
Compounded
USBD active
Power supply modes and regulators
Normal voltage mode
High voltage mode
Power supply supervisor
Power-fail comparator
POWER — Power control
Registers
TASKS_CONSTLAT
TASKS_LOWPWR
SUBSCRIBE_CONSTLAT
SUBSCRIBE_LOWPWR
EVENTS_POFWARN
EVENTS_SLEEPENTER
EVENTS_SLEEPEXIT
PUBLISH_POFWARN
PUBLISH_SLEEPENTER
PUBLISH_SLEEPEXIT
INTEN
INTENSET
INTENCLR
GPREGRET[n]
REGULATORS — Regulator control
Normal voltage mode
High voltage mode
External circuitry supply
GPIO levels
Registers
MAINREGSTATUS (Retained)
SYSTEMOFF
POFCON (Retained)
VREGMAIN.DCDCEN (Retained)
VREGRADIO.DCDCEN (Retained)
VREGH.DCDCEN (Retained)
VREGH.EXTSILENTEN (Retained)
Electrical specification
Recommended operating conditions
Regulator specifications, VREGH stage
Regulator startup times
Power-fail comparator
USBREG — USB regulator control
Registers
EVENTS_USBDETECTED
EVENTS_USBREMOVED
EVENTS_USBPWRRDY
PUBLISH_USBDETECTED
PUBLISH_USBREMOVED
PUBLISH_USBPWRRDY
INTEN
INTENSET
INTENCLR
USBREGSTATUS
Electrical specification
USB operating conditions
USB regulator specifications
VBUS detection specifications
VREQCTRL — Voltage request control
Registers
VREGRADIO.VREQH (Retained)
VREGRADIO.VREQHREADY
Electrical specification
VREQCTRL electrical specifications
RESET — Reset control
Power-on reset
Pin reset
Brownout reset
Wakeup from System OFF mode reset
Soft reset
Watchdog timer reset
Network Force-OFF
Retained registers
Application core reset behavior
Network core reset behavior
Registers
RESETREAS
NETWORK.FORCEOFF
Electrical specification
Application core startup times
Network core startup times
CLOCK — Clock control
HFCLK controller
Application core frequency scaling
32 MHz crystal oscillator (HFXO)
Audio oscillator
Overriding the automatic HFCLK control system
LFCLK controller
32.768 kHz RC oscillator (LFRC)
Calibrating the 32.768 kHz RC oscillator
32.768 kHz crystal oscillator (LFXO)
32.768 kHz synthesized from HFCLK (LFSYNT)
Overriding the automatic LFCLK control system
Registers
TASKS_HFCLKSTART
TASKS_HFCLKSTOP
TASKS_LFCLKSTART
TASKS_LFCLKSTOP
TASKS_CAL
TASKS_HFCLKAUDIOSTART
TASKS_HFCLKAUDIOSTOP
TASKS_HFCLK192MSTART
TASKS_HFCLK192MSTOP
SUBSCRIBE_HFCLKSTART
SUBSCRIBE_HFCLKSTOP
SUBSCRIBE_LFCLKSTART
SUBSCRIBE_LFCLKSTOP
SUBSCRIBE_CAL
SUBSCRIBE_HFCLKAUDIOSTART
SUBSCRIBE_HFCLKAUDIOSTOP
SUBSCRIBE_HFCLK192MSTART
SUBSCRIBE_HFCLK192MSTOP
EVENTS_HFCLKSTARTED
EVENTS_LFCLKSTARTED
EVENTS_DONE
EVENTS_HFCLKAUDIOSTARTED
EVENTS_HFCLK192MSTARTED
PUBLISH_HFCLKSTARTED
PUBLISH_LFCLKSTARTED
PUBLISH_DONE
PUBLISH_HFCLKAUDIOSTARTED
PUBLISH_HFCLK192MSTARTED
INTEN
INTENSET
INTENCLR
INTPEND
HFCLKRUN
HFCLKSTAT
LFCLKRUN
LFCLKSTAT
LFCLKSRCCOPY
HFCLKAUDIORUN
HFCLKAUDIOSTAT
HFCLK192MRUN
HFCLK192MSTAT
HFCLKSRC
LFCLKSRC
HFCLKCTRL
HFCLKAUDIO.FREQUENCY
HFCLKALWAYSRUN
LFCLKALWAYSRUN
HFCLKAUDIOALWAYSRUN
HFCLK192MSRC
HFCLK192MALWAYSRUN
HFCLK192MCTRL
Electrical specification
128 MHz clock source (HFCLK128M)
64 MHz clock source (HFCLK64M)
192 MHz clock source (HFCLK192M)
Audio clock source (HFCLKAUDIO)
32 kHz clock source (LFCLK)
OSCILLATORS — Oscillator control
High-frequency (32 MHz) crystal oscillator (HFXO)
Using internal capacitors
Low-frequency (32.768 kHz) crystal oscillator (LFXO)
Using internal capacitors
Low-frequency (32.768 kHz) external source
Registers
XOSC32MCAPS (Retained)
XOSC32KI.BYPASS (Retained)
XOSC32KI.INTCAP (Retained)
Electrical specification
32 MHz crystal oscillator (HFXO)
32.768 kHz crystal oscillator (LFXO)
Application core
Block diagram
CPU
Floating point interrupt
Electrical specification
CPU performance
CPU and support module configuration
Memory
Peripheral instantiation
Instantiation
Core components
CACHE — Instruction/data cache
Cache content
Profiling
Registers
PROFILING[n].IHIT
PROFILING[n].IMISS
PROFILING[n].DHIT
PROFILING[n].DMISS
ENABLE
INVALIDATE
ERASE
PROFILINGENABLE
PROFILINGCLEAR
MODE
DEBUGLOCK
ERASESTATUS
WRITELOCK
Electrical specification
Cache size
Registers
SET[n].WAY[o]
Registers
SET[n].WAY[o].DATA0
SET[n].WAY[o].DATA1
SET[n].WAY[o].DATA2
SET[n].WAY[o].DATA3
FICR — Factory information configuration registers
Registers
INFO
INFO.CONFIGID
INFO.DEVICEID[n]
INFO.PART
INFO.VARIANT
INFO.PACKAGE
INFO.RAM
INFO.FLASH
INFO.CODEPAGESIZE
INFO.CODESIZE
INFO.DEVICETYPE
TRIMCNF[n].ADDR
TRIMCNF[n].DATA
NFC.TAGHEADER0
NFC.TAGHEADER1
NFC.TAGHEADER2
NFC.TAGHEADER3
TRNG90B
TRNG90B.BYTES
TRNG90B.RCCUTOFF
TRNG90B.APCUTOFF
TRNG90B.STARTUP
TRNG90B.ROSC1
TRNG90B.ROSC2
TRNG90B.ROSC3
TRNG90B.ROSC4
XOSC32MTRIM
UICR — User information configuration registers
Registers
APPROTECT
VREGHVOUT
HFXOCNT
SECUREAPPROTECT
ERASEPROTECT
TINSTANCE
NFCPINS
OTP[n]
KEYSLOT.CONFIG[n].DEST
KEYSLOT.CONFIG[n].PERM
KEYSLOT.KEY[n].VALUE[o]
AHB multilayer
AHB multilayer priorities
Network core
Block diagram
CPU
Electrical specification
CPU performance
CPU and support module configuration
Memory
Peripheral instantiation
Core components
FICR — Factory information configuration registers
Registers
INFO
INFO.CONFIGID
INFO.DEVICEID[n]
INFO.PART
INFO.VARIANT
INFO.PACKAGE
INFO.RAM
INFO.FLASH
INFO.CODEPAGESIZE
INFO.CODESIZE
INFO.DEVICETYPE
ER[n]
IR[n]
DEVICEADDRTYPE
DEVICEADDR[n]
TRIMCNF[n].ADDR
TRIMCNF[n].DATA
UICR — User information configuration registers
Registers
APPROTECT
ERASEPROTECT
NRFFW[n]
CUSTOMER[n]
AHB multilayer
AHB multilayer priorities
Peripherals
Peripheral interface
Peripheral ID
Peripherals with shared ID
Peripheral registers
Bit set and clear
Tasks
Events
Publish and subscribe
Shortcuts
Interrupts
Interrupt clearing and disabling
Secure/non-secure peripherals
EasyDMA
EasyDMA error handling
EasyDMA array list
ACL — Access control lists
Registers
ACL[n].ADDR
ACL[n].SIZE
ACL[n].PERM
AAR — Accelerated address resolver
Shared resources
EasyDMA
Resolving a resolvable address
Example
IRK data structure
Registers
TASKS_START
TASKS_STOP
SUBSCRIBE_START
SUBSCRIBE_STOP
EVENTS_END
EVENTS_RESOLVED
EVENTS_NOTRESOLVED
PUBLISH_END
PUBLISH_RESOLVED
PUBLISH_NOTRESOLVED
INTENSET
INTENCLR
STATUS
ENABLE
NIRK
IRKPTR
ADDRPTR
SCRATCHPTR
Electrical specification
AAR Electrical Specification
CCM — AES CCM mode encryption
Shared resources
Keystream generation
Encryption
Decryption
AES CCM and RADIO concurrent operation
Encrypting packets on-the-fly in radio transmit mode
Decrypting packets on-the-fly in RADIO receive mode
CCM data structure
EasyDMA and ERROR event
Registers
TASKS_KSGEN
TASKS_CRYPT
TASKS_STOP
TASKS_RATEOVERRIDE
SUBSCRIBE_KSGEN
SUBSCRIBE_CRYPT
SUBSCRIBE_STOP
SUBSCRIBE_RATEOVERRIDE
EVENTS_ENDKSGEN
EVENTS_ENDCRYPT
EVENTS_ERROR (Deprecated)
PUBLISH_ENDKSGEN
PUBLISH_ENDCRYPT
PUBLISH_ERROR (Deprecated)
SHORTS
INTENSET
INTENCLR
MICSTATUS
ENABLE
MODE
CNFPTR
INPTR
OUTPTR
SCRATCHPTR
MAXPACKETSIZE
RATEOVERRIDE
HEADERMASK
Electrical specification
Timing specification
COMP — Comparator
Shared resources
Differential mode
Single-ended mode
Registers
TASKS_START
TASKS_STOP
TASKS_SAMPLE
SUBSCRIBE_START
SUBSCRIBE_STOP
SUBSCRIBE_SAMPLE
EVENTS_READY
EVENTS_DOWN
EVENTS_UP
EVENTS_CROSS
PUBLISH_READY
PUBLISH_DOWN
PUBLISH_UP
PUBLISH_CROSS
SHORTS
INTEN
INTENSET
INTENCLR
RESULT
ENABLE
PSEL
REFSEL
EXTREFSEL
TH
MODE
HYST
ISOURCE
Electrical specification
COMP Electrical Specification
COMP Current Source (ISOURCE) Specification
CRYPTOCELL — Arm TrustZone CryptoCell 312
Disclaimer
Usage
Security configuration
APB filtering
Cryptographic flow
Cryptographic key selection
Session keys
Key Management Unit (KMU) keys
Asymmetric keys
Internal memories
Direct memory access (DMA)
Power and clock
Interrupt handling
Standards
Registers
ENABLE
Accelerators
AES engine
Cryptographic flow
Registers
AES_KEY_0[n]
AES_KEY_1[n]
AES_IV_0[n]
AES_IV_1[n]
AES_CTR[n]
AES_BUSY
AES_CMAC_INIT
AES_REMAINING_BYTES
AES_CONTROL
AES_HW_FLAGS
AES_CTR_NO_INCREMENT
AES_SW_RESET
AES_CMAC_SIZE0_KICK
CHACHA engine
Cryptographic flow
Registers
CHACHA_CONTROL
CHACHA_VERSION
CHACHA_KEY[n]
CHACHA_IV[n]
CHACHA_BUSY
CHACHA_HW_FLAGS
CHACHA_BLOCK_CNT_LSB
CHACHA_BLOCK_CNT_MSB
CHACHA_SW_RESET
CHACHA_POLY1305_KEY[n]
CHACHA_ENDIANNESS
CHACHA_DEBUG
GHASH engine
Registers
GHASH_SUBKEY[n]
GHASH_IV[n]
GHASH_BUSY
GHASH_INIT
HASH engine
Cryptographic flow
Registers
HASH_H[n]
HASH_PAD_AUTO
HASH_XOR_DIN
HASH_INIT_STATE
HASH_SELECT
HASH_CONTROL
HASH_PAD
HASH_PAD_FORCE
HASH_CUR_LEN_0
HASH_CUR_LEN_1
HASH_HW_FLAGS
HASH_SW_RESET
HASH_ENDIANNESS
PKA engine
Virtual memory mapping
Engine operations
OPCODE overview
Pipeline configuration
PKA SRAM
Cryptographic flow
Registers
MEMORY_MAP[n]
OPCODE
N_NP_T0_T1_ADDR
PKA_STATUS
PKA_SW_RESET
PKA_L[n]
PKA_PIPE
PKA_DONE
PKA_VERSION
PKA_SRAM_WADDR
PKA_SRAM_WDATA
PKA_SRAM_RDATA
PKA_SRAM_WCLEAR
PKA_SRAM_RADDR
RNG engine
Ring oscillator length configuration
RNG SRAM
TRNG hardware tests
von Neumann Corrector
Continuous random number generation test
Autocorrelation test
Cryptographic flow
Registers
RNG_IMR
RNG_ISR
RNG_ICR
TRNG_CONFIG
TRNG_VALID
EHR_DATA[n]
NOISE_SOURCE
SAMPLE_CNT
AUTOCORR_STATISTIC
TRNG_DEBUG
RNG_SW_RESET
RNG_BUSY
TRNG_RESET
RNG_HW_FLAGS
RNG_CLK
RNG_DMA
RNG_DMA_ROSC_LEN
RNG_DMA_SRAM_ADDR
RNG_DMA_SAMPLES_NUM
RNG_WATCHDOG_VAL
RNG_DMA_BUSY
Host integration
AHB interface
Registers
AHBM_SINGLES
AHBM_HPROT
AHBM_HMASTLOCK
AHBM_HNONSEC
AO interface
Registers
AO_APB_FILTERING
CC_SW_RESET
CTL interface
Registers
CRYPTO_CTL
CRYPTO_BUSY
HASH_BUSY
CONTEXT_ID
DIN DMA engine
Registers
DIN_BUFFER
DIN_DMA_MEM_BUSY
SRC_MEM_ADDR
SRC_MEM_SIZE
SRC_SRAM_ADDR
SRC_SRAM_SIZE
DIN_DMA_SRAM_BUSY
DIN_DMA_SRAM_ENDIANNESS
DIN_SW_RESET
DIN_CPU_DATA
DIN_WRITE_ALIGN
DIN_FIFO_EMPTY
DIN_FIFO_RESET
DOUT DMA engine
Registers
DOUT_BUFFER
DOUT_DMA_MEM_BUSY
DST_MEM_ADDR
DST_MEM_SIZE
DST_SRAM_ADDR
DST_SRAM_SIZE
DOUT_DMA_SRAM_BUSY
DOUT_DMA_SRAM_ENDIANNESS
DOUT_READ_ALIGN
DOUT_FIFO_EMPTY
DOUT_SW_RESET
HOST register interface
Registers
IRR
IMR
ICR
ENDIANNESS
HOST_SIGNATURE
HOST_BOOT
HOST_CC_IS_IDLE
HOST_POWERDOWN
RNG SRAM interface
Registers
SRAM_DATA
SRAM_ADDR
SRAM_DATA_READY
MISC interface
Registers
AES_CLK
HASH_CLK
PKA_CLK
DMA_CLK
CLK_STATUS
CHACHA_CLK
DCNF — Domain configuration
Protection
Registers
CPUID
EXTPERI[n].PROTECT
EXTRAM[n].PROTECT
EXTCODE[n].PROTECT
DPPI — Distributed programmable peripheral interconnect
Subscribing to and publishing on channels
DPPI controller (DPPIC)
Connection examples
Special considerations for a system implementing TrustZone for Cortex-M processors
Registers
TASKS_CHG[n]
TASKS_CHG[n].EN
TASKS_CHG[n].DIS
SUBSCRIBE_CHG[n]
SUBSCRIBE_CHG[n].EN
SUBSCRIBE_CHG[n].DIS
CHEN
CHENSET
CHENCLR
CHG[n]
ECB — AES electronic codebook mode encryption
Shared resources
EasyDMA
ECB data structure
Registers
TASKS_STARTECB
TASKS_STOPECB
SUBSCRIBE_STARTECB
SUBSCRIBE_STOPECB
EVENTS_ENDECB
EVENTS_ERRORECB
PUBLISH_ENDECB
PUBLISH_ERRORECB
INTENSET
INTENCLR
ECBDATAPTR
Electrical specification
ECB Electrical Specification
EGU — Event generator unit
Registers
TASKS_TRIGGER[n]
SUBSCRIBE_TRIGGER[n]
EVENTS_TRIGGERED[n]
PUBLISH_TRIGGERED[n]
INTEN
INTENSET
INTENCLR
Electrical specification
EGU Electrical Specification
FPU — Floating point unit (FPU) exceptions
Registers
EVENTS_INVALIDOPERATION
EVENTS_DIVIDEBYZERO
EVENTS_OVERFLOW
EVENTS_UNDERFLOW
EVENTS_INEXACT
EVENTS_DENORMALINPUT
INTEN
INTENSET
INTENCLR
GPIO — General purpose input/output
Assigning pins between cores, peripherals, or subsystems
Pin configuration
Pin sense mechanism
GPIO security
Registers
OUT (Retained)
OUTSET
OUTCLR
IN
DIR (Retained)
DIRSET
DIRCLR
LATCH (Retained)
DETECTMODE (Retained)
DETECTMODE_SEC (Retained)
PIN_CNF[n]
Electrical specification
GPIO Electrical Specification
GPIOTE — GPIO tasks and events
Pin events and tasks
Port event
Tasks and events pin configuration
Low power
Registers
TASKS_OUT[n]
TASKS_SET[n]
TASKS_CLR[n]
SUBSCRIBE_OUT[n]
SUBSCRIBE_SET[n]
SUBSCRIBE_CLR[n]
EVENTS_IN[n]
EVENTS_PORT
PUBLISH_IN[n]
PUBLISH_PORT
INTENSET
INTENCLR
LATENCY
CONFIG[n]
I2S — Inter-IC sound interface
Mode
Transmitting and receiving
Left right clock (LRCK)
Serial clock (SCK)
Master clock (MCK)
Clock source selection
Configuration examples
Width, alignment and format
EasyDMA
Module operation
Pin configuration
Registers
TASKS_START
TASKS_STOP
SUBSCRIBE_START
SUBSCRIBE_STOP
EVENTS_RXPTRUPD
EVENTS_STOPPED
EVENTS_TXPTRUPD
EVENTS_FRAMESTART
PUBLISH_RXPTRUPD
PUBLISH_STOPPED
PUBLISH_TXPTRUPD
PUBLISH_FRAMESTART
INTEN
INTENSET
INTENCLR
ENABLE
CONFIG.MODE
CONFIG.RXEN
CONFIG.TXEN
CONFIG.MCKEN
CONFIG.MCKFREQ
CONFIG.RATIO
CONFIG.SWIDTH
CONFIG.ALIGN
CONFIG.FORMAT
CONFIG.CHANNELS
CONFIG.CLKCONFIG
RXD.PTR
TXD.PTR
RXTXD.MAXCNT
PSEL.MCK
PSEL.SCK
PSEL.LRCK
PSEL.SDIN
PSEL.SDOUT
Electrical specification
I2S timing specification
IPC — Interprocessor communication
IPC and PPI connections
Registers
TASKS_SEND[n]
SUBSCRIBE_SEND[n]
EVENTS_RECEIVE[n]
PUBLISH_RECEIVE[n]
INTEN
INTENSET
INTENCLR
INTPEND
SEND_CNF[n]
RECEIVE_CNF[n]
GPMEM[n]
Electrical specification
IPC Electrical Specification
KMU — Key management unit
Functional view
Access control
Protecting the UICR content
Usage
OTP
Key storage
Selecting a key slot
Writing to a key slot
Reading a key value
Push over secure APB
Revoking the key slots
STATUS register
Registers
TASKS_PUSH_KEYSLOT
EVENTS_KEYSLOT_PUSHED
EVENTS_KEYSLOT_REVOKED
EVENTS_KEYSLOT_ERROR
INTEN
INTENSET
INTENCLR
INTPEND
STATUS
SELECTKEYSLOT
LPCOMP — Low-power comparator
Shared resources
Pin configuration
Registers
TASKS_START
TASKS_STOP
TASKS_SAMPLE
SUBSCRIBE_START
SUBSCRIBE_STOP
SUBSCRIBE_SAMPLE
EVENTS_READY
EVENTS_DOWN
EVENTS_UP
EVENTS_CROSS
PUBLISH_READY
PUBLISH_DOWN
PUBLISH_UP
PUBLISH_CROSS
SHORTS
INTENSET
INTENCLR
RESULT
ENABLE
PSEL
REFSEL
EXTREFSEL
ANADETECT
HYST
Electrical specification
LPCOMP Electrical Specification
MUTEX — Mutual exclusive peripheral
Registers
MUTEX[n]
NFCT — Near field communication tag
Overview
Operating states
Pin configuration
EasyDMA
Frame assembler
Frame disassembler
Frame timing controller
Collision resolution
Antenna interface
NFCT antenna recommendations
Battery protection
Digital Modulation Signal
References
Registers
TASKS_ACTIVATE
TASKS_DISABLE
TASKS_SENSE
TASKS_STARTTX
TASKS_ENABLERXDATA
TASKS_GOIDLE
TASKS_GOSLEEP
SUBSCRIBE_ACTIVATE
SUBSCRIBE_DISABLE
SUBSCRIBE_SENSE
SUBSCRIBE_STARTTX
SUBSCRIBE_ENABLERXDATA
SUBSCRIBE_GOIDLE
SUBSCRIBE_GOSLEEP
EVENTS_READY
EVENTS_FIELDDETECTED
EVENTS_FIELDLOST
EVENTS_TXFRAMESTART
EVENTS_TXFRAMEEND
EVENTS_RXFRAMESTART
EVENTS_RXFRAMEEND
EVENTS_ERROR
EVENTS_RXERROR
EVENTS_ENDRX
EVENTS_ENDTX
EVENTS_AUTOCOLRESSTARTED
EVENTS_COLLISION
EVENTS_SELECTED
EVENTS_STARTED
PUBLISH_READY
PUBLISH_FIELDDETECTED
PUBLISH_FIELDLOST
PUBLISH_TXFRAMESTART
PUBLISH_TXFRAMEEND
PUBLISH_RXFRAMESTART
PUBLISH_RXFRAMEEND
PUBLISH_ERROR
PUBLISH_RXERROR
PUBLISH_ENDRX
PUBLISH_ENDTX
PUBLISH_AUTOCOLRESSTARTED
PUBLISH_COLLISION
PUBLISH_SELECTED
PUBLISH_STARTED
SHORTS
INTEN
INTENSET
INTENCLR
ERRORSTATUS
FRAMESTATUS.RX
NFCTAGSTATE
SLEEPSTATE
FIELDPRESENT
FRAMEDELAYMIN
FRAMEDELAYMAX
FRAMEDELAYMODE
PACKETPTR
MAXLEN
TXD.FRAMECONFIG
TXD.AMOUNT
RXD.FRAMECONFIG
RXD.AMOUNT
MODULATIONCTRL
MODULATIONPSEL
NFCID1_LAST
NFCID1_2ND_LAST
NFCID1_3RD_LAST
AUTOCOLRESCONFIG
SENSRES
SELRES
Electrical specification
NFCT Electrical Specification
NFCT Timing Parameters
NVMC — Non-volatile memory controller
Writing to flash
Erasing a secure page in flash
Erasing a non-secure page in flash
Writing to user information configuration registers (UICR)
Erase all
NVMC protection mechanisms
NVMC blocking
NVMC power failure protection
Cache
Registers
READY
READYNEXT
CONFIG
ERASEALL
ERASEPAGEPARTIALCFG
ICACHECNF
IHIT
IMISS
CONFIGNS
WRITEUICRNS
Electrical specification
Flash programming
Cache size
PDM — Pulse density modulation interface
Master clock source selection
Master clock generator
Module operation
Decimation filter
EasyDMA
Hardware example
Pin configuration
Registers
TASKS_START
TASKS_STOP
SUBSCRIBE_START
SUBSCRIBE_STOP
EVENTS_STARTED
EVENTS_STOPPED
EVENTS_END
PUBLISH_STARTED
PUBLISH_STOPPED
PUBLISH_END
INTEN
INTENSET
INTENCLR
ENABLE
PDMCLKCTRL
MODE
GAINL
GAINR
RATIO
PSEL.CLK
PSEL.DIN
MCLKCONFIG
SAMPLE.PTR
SAMPLE.MAXCNT
Electrical specification
PDM Electrical Specification
PWM — Pulse width modulation
Wave counter
Decoder with EasyDMA
Limitations
Pin configuration
Registers
TASKS_STOP
TASKS_SEQSTART[n]
TASKS_NEXTSTEP
SUBSCRIBE_STOP
SUBSCRIBE_SEQSTART[n]
SUBSCRIBE_NEXTSTEP
EVENTS_STOPPED
EVENTS_SEQSTARTED[n]
EVENTS_SEQEND[n]
EVENTS_PWMPERIODEND
EVENTS_LOOPSDONE
PUBLISH_STOPPED
PUBLISH_SEQSTARTED[n]
PUBLISH_SEQEND[n]
PUBLISH_PWMPERIODEND
PUBLISH_LOOPSDONE
SHORTS
INTEN
INTENSET
INTENCLR
ENABLE
MODE
COUNTERTOP
PRESCALER
DECODER
LOOP
SEQ[n].PTR
SEQ[n].CNT
SEQ[n].REFRESH
SEQ[n].ENDDELAY
PSEL.OUT[n]
QDEC — Quadrature decoder
Sampling and decoding
LED output
Debounce filters
Accumulators
Output/input pins
Pin configuration
Registers
TASKS_START
TASKS_STOP
TASKS_READCLRACC
TASKS_RDCLRACC
TASKS_RDCLRDBL
SUBSCRIBE_START
SUBSCRIBE_STOP
SUBSCRIBE_READCLRACC
SUBSCRIBE_RDCLRACC
SUBSCRIBE_RDCLRDBL
EVENTS_SAMPLERDY
EVENTS_REPORTRDY
EVENTS_ACCOF
EVENTS_DBLRDY
EVENTS_STOPPED
PUBLISH_SAMPLERDY
PUBLISH_REPORTRDY
PUBLISH_ACCOF
PUBLISH_DBLRDY
PUBLISH_STOPPED
SHORTS
INTENSET
INTENCLR
ENABLE
LEDPOL
SAMPLEPER
SAMPLE
REPORTPER
ACC
ACCREAD
PSEL.LED
PSEL.A
PSEL.B
DBFEN
LEDPRE
ACCDBL
ACCDBLREAD
Electrical specification
QDEC Electrical Specification
QSPI — Quad serial peripheral interface
Configuring QSPI
Write operation
Read operation
Erase operation
Execute in place
Encryption
Sending custom instructions
Long frame mode
Deep power-down mode
Instruction set
Interface description
Registers
TASKS_ACTIVATE
TASKS_READSTART
TASKS_WRITESTART
TASKS_ERASESTART
TASKS_DEACTIVATE
SUBSCRIBE_ACTIVATE
SUBSCRIBE_READSTART
SUBSCRIBE_WRITESTART
SUBSCRIBE_ERASESTART
SUBSCRIBE_DEACTIVATE
EVENTS_READY
PUBLISH_READY
INTEN
INTENSET
INTENCLR
ENABLE
READ.SRC
READ.DST
READ.CNT
WRITE.DST
WRITE.SRC
WRITE.CNT
ERASE.PTR
ERASE.LEN
PSEL.SCK
PSEL.CSN
PSEL.IO0
PSEL.IO1
PSEL.IO2
PSEL.IO3
XIPOFFSET
IFCONFIG0
XIPEN
XIP_ENC.KEY0
XIP_ENC.KEY1
XIP_ENC.KEY2
XIP_ENC.KEY3
XIP_ENC.NONCE0
XIP_ENC.NONCE1
XIP_ENC.NONCE2
XIP_ENC.ENABLE
DMA_ENC.KEY0
DMA_ENC.KEY1
DMA_ENC.KEY2
DMA_ENC.KEY3
DMA_ENC.NONCE0
DMA_ENC.NONCE1
DMA_ENC.NONCE2
DMA_ENC.ENABLE
IFCONFIG1
STATUS
DPMDUR
ADDRCONF
CINSTRCONF
CINSTRDAT0
CINSTRDAT1
IFTIMING
Electrical specification
Timing specification
RADIO — 2.4 GHz radio
Packet configuration
Address configuration
Data whitening
CRC
Radio states
Transmit sequence
Receive sequence
Received signal strength indicator (RSSI)
Interframe spacing (IFS)
Device address match
Bit counter
Direction finding
CTE format
Mode
Inline configuration
Manual configuration
Receive- and transmit sequences
Antenna switching
IQ sampling
IEEE 802.15.4 operation
Packet structure
Operating frequencies
Energy detection (ED)
Clear channel assessment (CCA)
Cyclic redundancy check (CRC)
Transmit sequence
Receive sequence
Interframe spacing (IFS)
EasyDMA
Registers
TASKS_TXEN
TASKS_RXEN
TASKS_START
TASKS_STOP
TASKS_DISABLE
TASKS_RSSISTART
TASKS_RSSISTOP
TASKS_BCSTART
TASKS_BCSTOP
TASKS_EDSTART
TASKS_EDSTOP
TASKS_CCASTART
TASKS_CCASTOP
SUBSCRIBE_TXEN
SUBSCRIBE_RXEN
SUBSCRIBE_START
SUBSCRIBE_STOP
SUBSCRIBE_DISABLE
SUBSCRIBE_RSSISTART
SUBSCRIBE_RSSISTOP
SUBSCRIBE_BCSTART
SUBSCRIBE_BCSTOP
SUBSCRIBE_EDSTART
SUBSCRIBE_EDSTOP
SUBSCRIBE_CCASTART
SUBSCRIBE_CCASTOP
EVENTS_READY
EVENTS_ADDRESS
EVENTS_PAYLOAD
EVENTS_END
EVENTS_DISABLED
EVENTS_DEVMATCH
EVENTS_DEVMISS
EVENTS_RSSIEND
EVENTS_BCMATCH
EVENTS_CRCOK
EVENTS_CRCERROR
EVENTS_FRAMESTART
EVENTS_EDEND
EVENTS_EDSTOPPED
EVENTS_CCAIDLE
EVENTS_CCABUSY
EVENTS_CCASTOPPED
EVENTS_RATEBOOST
EVENTS_TXREADY
EVENTS_RXREADY
EVENTS_MHRMATCH
EVENTS_SYNC
EVENTS_PHYEND
EVENTS_CTEPRESENT
PUBLISH_READY
PUBLISH_ADDRESS
PUBLISH_PAYLOAD
PUBLISH_END
PUBLISH_DISABLED
PUBLISH_DEVMATCH
PUBLISH_DEVMISS
PUBLISH_RSSIEND
PUBLISH_BCMATCH
PUBLISH_CRCOK
PUBLISH_CRCERROR
PUBLISH_FRAMESTART
PUBLISH_EDEND
PUBLISH_EDSTOPPED
PUBLISH_CCAIDLE
PUBLISH_CCABUSY
PUBLISH_CCASTOPPED
PUBLISH_RATEBOOST
PUBLISH_TXREADY
PUBLISH_RXREADY
PUBLISH_MHRMATCH
PUBLISH_SYNC
PUBLISH_PHYEND
PUBLISH_CTEPRESENT
SHORTS
INTENSET
INTENCLR
CRCSTATUS
RXMATCH
RXCRC
DAI
PDUSTAT
CTESTATUS
DFESTATUS
PACKETPTR
FREQUENCY
TXPOWER
MODE
PCNF0
PCNF1
BASE0
BASE1
PREFIX0
PREFIX1
TXADDRESS
RXADDRESSES
CRCCNF
CRCPOLY
CRCINIT
TIFS
RSSISAMPLE
STATE
DATAWHITEIV
BCC
DAB[n]
DAP[n]
DACNF
MHRMATCHCONF
MHRMATCHMAS
MODECNF0
SFD
EDCNT
EDSAMPLE
CCACTRL
DFEMODE
CTEINLINECONF
DFECTRL1
DFECTRL2
SWITCHPATTERN
CLEARPATTERN
PSEL.DFEGPIO[n]
DFEPACKET
DFEPACKET.PTR
DFEPACKET.MAXCNT
DFEPACKET.AMOUNT
POWER
Electrical specification
General radio characteristics
Radio current consumption (transmitter)
Radio current consumption (receiver)
Transmitter specification
Receiver operation
Receiver selectivity
Receiver intermodulation
Radio timing
Received signal strength indicator (RSSI) specifications
Jitter
IEEE 802.15.4 mode energy detection constants
RNG — Random number generator
Bias correction
Speed
Registers
TASKS_START
TASKS_STOP
SUBSCRIBE_START
SUBSCRIBE_STOP
EVENTS_VALRDY
PUBLISH_VALRDY
SHORTS
INTENSET
INTENCLR
CONFIG
VALUE
Electrical specification
RNG Electrical Specification
RTC — Real-time counter
Clock source
Resolution versus overflow and the prescaler
Counter register
Reading the counter register
Overflow
Tick event
Event control
Capture
Compare
Task and event jitter/delay
Registers
TASKS_START
TASKS_STOP
TASKS_CLEAR
TASKS_TRIGOVRFLW
TASKS_CAPTURE[n]
SUBSCRIBE_START
SUBSCRIBE_STOP
SUBSCRIBE_CLEAR
SUBSCRIBE_TRIGOVRFLW
SUBSCRIBE_CAPTURE[n]
EVENTS_TICK
EVENTS_OVRFLW
EVENTS_COMPARE[n]
PUBLISH_TICK
PUBLISH_OVRFLW
PUBLISH_COMPARE[n]
SHORTS
INTENSET
INTENCLR
EVTEN
EVTENSET
EVTENCLR
COUNTER
PRESCALER
CC[n]
SAADC — Successive approximation analog-to-digital converter
Shared resources
Overview
Digital output
Analog inputs and channels
Operation modes
One-shot mode
Continuous mode
Oversampling
Scan mode
EasyDMA
Resistor ladder
Reference
Acquisition time
Limits event monitoring
Registers
TASKS_START
TASKS_SAMPLE
TASKS_STOP
TASKS_CALIBRATEOFFSET
SUBSCRIBE_START
SUBSCRIBE_SAMPLE
SUBSCRIBE_STOP
SUBSCRIBE_CALIBRATEOFFSET
EVENTS_STARTED
EVENTS_END
EVENTS_DONE
EVENTS_RESULTDONE
EVENTS_CALIBRATEDONE
EVENTS_STOPPED
EVENTS_CH[n]
EVENTS_CH[n].LIMITH
EVENTS_CH[n].LIMITL
PUBLISH_STARTED
PUBLISH_END
PUBLISH_DONE
PUBLISH_RESULTDONE
PUBLISH_CALIBRATEDONE
PUBLISH_STOPPED
PUBLISH_CH[n]
PUBLISH_CH[n].LIMITH
PUBLISH_CH[n].LIMITL
INTEN
INTENSET
INTENCLR
STATUS
ENABLE
CH[n].PSELP
CH[n].PSELN
CH[n].CONFIG
CH[n].LIMIT
RESOLUTION
OVERSAMPLE
SAMPLERATE
RESULT
RESULT.PTR
RESULT.MAXCNT
RESULT.AMOUNT
Electrical specification
SAADC Electrical Specification
Performance factors
SPIM — Serial peripheral interface master with EasyDMA
SPI master transaction sequence
D/CX functionality
Pin configuration
Shared resources
EasyDMA
Low power
Registers
TASKS_START
TASKS_STOP
TASKS_SUSPEND
TASKS_RESUME
SUBSCRIBE_START
SUBSCRIBE_STOP
SUBSCRIBE_SUSPEND
SUBSCRIBE_RESUME
EVENTS_STOPPED
EVENTS_ENDRX
EVENTS_END
EVENTS_ENDTX
EVENTS_STARTED
PUBLISH_STOPPED
PUBLISH_ENDRX
PUBLISH_END
PUBLISH_ENDTX
PUBLISH_STARTED
SHORTS
INTENSET
INTENCLR
STALLSTAT
ENABLE
PSEL.SCK
PSEL.MOSI
PSEL.MISO
PSEL.CSN
FREQUENCY
RXD
RXD.PTR
RXD.MAXCNT
RXD.AMOUNT
RXD.LIST
TXD
TXD.PTR
TXD.MAXCNT
TXD.AMOUNT
TXD.LIST
CONFIG
IFTIMING.RXDELAY
IFTIMING.CSNDUR
CSNPOL
PSELDCX
DCXCNT
ORC
Electrical specification
Timing specifications
SPIS — Serial peripheral interface slave with EasyDMA
Shared resources
EasyDMA
SPI slave operation
Semaphore operation
Pin configuration
Registers
TASKS_ACQUIRE
TASKS_RELEASE
SUBSCRIBE_ACQUIRE
SUBSCRIBE_RELEASE
EVENTS_END
EVENTS_ENDRX
EVENTS_ACQUIRED
PUBLISH_END
PUBLISH_ENDRX
PUBLISH_ACQUIRED
SHORTS
INTENSET
INTENCLR
SEMSTAT
STATUS
ENABLE
PSEL.SCK
PSEL.MISO
PSEL.MOSI
PSEL.CSN
RXD.PTR
RXD.MAXCNT
RXD.AMOUNT
RXD.LIST
TXD.PTR
TXD.MAXCNT
TXD.AMOUNT
TXD.LIST
CONFIG
DEF
ORC
Electrical specification
SPIS slave interface electrical specifications
Serial Peripheral Interface Slave (SPIS) timing specifications
SPU — System protection unit
General concepts
Special considerations for Arm TrustZone for Cortex-M enabled system
Flash access control
Non-secure callable (NSC) region definition in flash
Flash access error reporting
UICR and FICR protections
RAM access control
Non-secure callable (NSC) region definition in RAM
RAM access error reporting
Peripheral access control
Peripherals with split security
Peripheral address mapping
Special considerations for peripherals with DMA master
Peripheral access error reporting
Pin access control
DPPI access control
Special considerations regarding the DPPIC configuration registers
External domain access control
Arm TrustZone for Cortex-M ID allocation
Registers
EVENTS_RAMACCERR
EVENTS_FLASHACCERR
EVENTS_PERIPHACCERR
PUBLISH_RAMACCERR
PUBLISH_FLASHACCERR
PUBLISH_PERIPHACCERR
INTEN
INTENSET
INTENCLR
CAP
CPULOCK
EXTDOMAIN[n].PERM
DPPI[n].PERM
DPPI[n].LOCK
GPIOPORT[n].PERM
GPIOPORT[n].LOCK
FLASHNSC[n].REGION
FLASHNSC[n].SIZE
RAMNSC[n].REGION
RAMNSC[n].SIZE
FLASHREGION[n].PERM
RAMREGION[n].PERM
PERIPHID[n].PERM
SWI — Software interrupts
Registers
TEMP — Temperature sensor
Registers
TASKS_START
TASKS_STOP
SUBSCRIBE_START
SUBSCRIBE_STOP
EVENTS_DATARDY
PUBLISH_DATARDY
INTENSET
INTENCLR
TEMP
A0
A1
A2
A3
A4
A5
B0
B1
B2
B3
B4
B5
T0
T1
T2
T3
T4
Electrical specification
Temperature Sensor Electrical Specification
TIMER — Timer/counter
Capture
Compare
Task delays
Task priority
Registers
TASKS_START
TASKS_STOP
TASKS_COUNT
TASKS_CLEAR
TASKS_SHUTDOWN (Deprecated)
TASKS_CAPTURE[n]
SUBSCRIBE_START
SUBSCRIBE_STOP
SUBSCRIBE_COUNT
SUBSCRIBE_CLEAR
SUBSCRIBE_SHUTDOWN (Deprecated)
SUBSCRIBE_CAPTURE[n]
EVENTS_COMPARE[n]
PUBLISH_COMPARE[n]
SHORTS
INTEN
INTENSET
INTENCLR
MODE
BITMODE
PRESCALER
CC[n]
ONESHOTEN[n]
TWIM — I2C compatible two-wire interface master with EasyDMA
Shared resources
EasyDMA
Master write sequence
Master read sequence
Master repeated start sequence
Low power
Master mode pin configuration
Registers
TASKS_STARTRX
TASKS_STARTTX
TASKS_STOP
TASKS_SUSPEND
TASKS_RESUME
SUBSCRIBE_STARTRX
SUBSCRIBE_STARTTX
SUBSCRIBE_STOP
SUBSCRIBE_SUSPEND
SUBSCRIBE_RESUME
EVENTS_STOPPED
EVENTS_ERROR
EVENTS_SUSPENDED
EVENTS_RXSTARTED
EVENTS_TXSTARTED
EVENTS_LASTRX
EVENTS_LASTTX
PUBLISH_STOPPED
PUBLISH_ERROR
PUBLISH_SUSPENDED
PUBLISH_RXSTARTED
PUBLISH_TXSTARTED
PUBLISH_LASTRX
PUBLISH_LASTTX
SHORTS
INTEN
INTENSET
INTENCLR
ERRORSRC
ENABLE
PSEL.SCL
PSEL.SDA
FREQUENCY
RXD
RXD.PTR
RXD.MAXCNT
RXD.AMOUNT
RXD.LIST
TXD
TXD.PTR
TXD.MAXCNT
TXD.AMOUNT
TXD.LIST
ADDRESS
Electrical specification
TWIM interface electrical specifications
Two Wire Interface Master (TWIM) timing specifications
Pullup resistor
TWIS — I2C compatible two-wire interface slave with EasyDMA
Shared resources
EasyDMA
TWIS responding to a read command
TWIS responding to a write command
Master repeated start sequence
Terminating an ongoing TWI transaction
Low power
Slave mode pin configuration
Registers
TASKS_STOP
TASKS_SUSPEND
TASKS_RESUME
TASKS_PREPARERX
TASKS_PREPARETX
SUBSCRIBE_STOP
SUBSCRIBE_SUSPEND
SUBSCRIBE_RESUME
SUBSCRIBE_PREPARERX
SUBSCRIBE_PREPARETX
EVENTS_STOPPED
EVENTS_ERROR
EVENTS_RXSTARTED
EVENTS_TXSTARTED
EVENTS_WRITE
EVENTS_READ
PUBLISH_STOPPED
PUBLISH_ERROR
PUBLISH_RXSTARTED
PUBLISH_TXSTARTED
PUBLISH_WRITE
PUBLISH_READ
SHORTS
INTEN
INTENSET
INTENCLR
ERRORSRC
MATCH
ENABLE
PSEL.SCL
PSEL.SDA
RXD
RXD.PTR
RXD.MAXCNT
RXD.AMOUNT
RXD.LIST
TXD
TXD.PTR
TXD.MAXCNT
TXD.AMOUNT
TXD.LIST
ADDRESS[n]
CONFIG
ORC
Electrical specification
TWIS slave timing specifications
UARTE — Universal asynchronous receiver/transmitter with EasyDMA
EasyDMA
Transmission
Reception
Error conditions
Using the UARTE without flow control
Parity and stop bit configuration
Low power
Pin configuration
Registers
TASKS_STARTRX
TASKS_STOPRX
TASKS_STARTTX
TASKS_STOPTX
TASKS_FLUSHRX
SUBSCRIBE_STARTRX
SUBSCRIBE_STOPRX
SUBSCRIBE_STARTTX
SUBSCRIBE_STOPTX
SUBSCRIBE_FLUSHRX
EVENTS_CTS
EVENTS_NCTS
EVENTS_RXDRDY
EVENTS_ENDRX
EVENTS_TXDRDY
EVENTS_ENDTX
EVENTS_ERROR
EVENTS_RXTO
EVENTS_RXSTARTED
EVENTS_TXSTARTED
EVENTS_TXSTOPPED
PUBLISH_CTS
PUBLISH_NCTS
PUBLISH_RXDRDY
PUBLISH_ENDRX
PUBLISH_TXDRDY
PUBLISH_ENDTX
PUBLISH_ERROR
PUBLISH_RXTO
PUBLISH_RXSTARTED
PUBLISH_TXSTARTED
PUBLISH_TXSTOPPED
SHORTS
INTEN
INTENSET
INTENCLR
ERRORSRC
ENABLE
PSEL.RTS
PSEL.TXD
PSEL.CTS
PSEL.RXD
BAUDRATE
RXD
RXD.PTR
RXD.MAXCNT
RXD.AMOUNT
TXD
TXD.PTR
TXD.MAXCNT
TXD.AMOUNT
CONFIG
Electrical specification
UARTE electrical specification
USBD — Universal serial bus device
USB device states
USB terminology
USB pins
USBD power-up sequence
USB reset
USB suspend and resume
Entering suspend
Host-initiated resume
Device-initiated remote wake-up
EasyDMA
Control transfers
Control read transfer
Control write transfer
Bulk and interrupt transactions
Bulk and interrupt IN transaction
Bulk and interrupt OUT transaction
Isochronous transactions
Isochronous IN transaction
Isochronous OUT transaction
USB register access limitations
Registers
TASKS_STARTEPIN[n]
TASKS_STARTISOIN
TASKS_STARTEPOUT[n]
TASKS_STARTISOOUT
TASKS_EP0RCVOUT
TASKS_EP0STATUS
TASKS_EP0STALL
TASKS_DPDMDRIVE
TASKS_DPDMNODRIVE
SUBSCRIBE_STARTEPIN[n]
SUBSCRIBE_STARTISOIN
SUBSCRIBE_STARTEPOUT[n]
SUBSCRIBE_STARTISOOUT
SUBSCRIBE_EP0RCVOUT
SUBSCRIBE_EP0STATUS
SUBSCRIBE_EP0STALL
SUBSCRIBE_DPDMDRIVE
SUBSCRIBE_DPDMNODRIVE
EVENTS_USBRESET
EVENTS_STARTED
EVENTS_ENDEPIN[n]
EVENTS_EP0DATADONE
EVENTS_ENDISOIN
EVENTS_ENDEPOUT[n]
EVENTS_ENDISOOUT
EVENTS_SOF
EVENTS_USBEVENT
EVENTS_EP0SETUP
EVENTS_EPDATA
PUBLISH_USBRESET
PUBLISH_STARTED
PUBLISH_ENDEPIN[n]
PUBLISH_EP0DATADONE
PUBLISH_ENDISOIN
PUBLISH_ENDEPOUT[n]
PUBLISH_ENDISOOUT
PUBLISH_SOF
PUBLISH_USBEVENT
PUBLISH_EP0SETUP
PUBLISH_EPDATA
SHORTS
INTEN
INTENSET
INTENCLR
EVENTCAUSE
HALTED.EPIN[n]
HALTED.EPOUT[n]
EPSTATUS
EPDATASTATUS
USBADDR
BMREQUESTTYPE
BREQUEST
WVALUEL
WVALUEH
WINDEXL
WINDEXH
WLENGTHL
WLENGTHH
SIZE.EPOUT[n]
SIZE.ISOOUT
ENABLE
USBPULLUP
DPDMVALUE
DTOGGLE
EPINEN
EPOUTEN
EPSTALL
ISOSPLIT
FRAMECNTR
LOWPOWER
ISOINCONFIG
EPIN[n].PTR
EPIN[n].MAXCNT
EPIN[n].AMOUNT
ISOIN.PTR
ISOIN.MAXCNT
ISOIN.AMOUNT
EPOUT[n].PTR
EPOUT[n].MAXCNT
EPOUT[n].AMOUNT
ISOOUT.PTR
ISOOUT.MAXCNT
ISOOUT.AMOUNT
Electrical specification
USB Electrical Specification
VMC — Volatile memory controller
RAM power states
Registers
RAM[n].POWER
RAM[n].POWERSET
RAM[n].POWERCLR
WDT — Watchdog timer
Reload criteria
Temporarily pausing the watchdog
Watchdog reset
Stopping the watchdog
Registers
TASKS_START
TASKS_STOP
SUBSCRIBE_START
SUBSCRIBE_STOP
EVENTS_TIMEOUT
EVENTS_STOPPED
PUBLISH_TIMEOUT
PUBLISH_STOPPED
INTENSET
INTENCLR
NMIENSET
NMIENCLR
RUNSTATUS
REQSTATUS
CRV
RREN
CONFIG
TSEN
RR[n]
Electrical specification
Watchdog Timer Electrical Specification
Debug and trace
DAP — Debug access port
Registers
TARGETID
DLPIDR
Electrical specification
SW-DP
Trace port
Access port protection
Debug Interface mode
Real-time debug
ROM tables
Cross-trigger network
Multidrop serial wire debug
Trace
Enabling the trace port
CTRL-AP - Control access port
Reset request
Erase all
Mailbox interface
Disabling erase protection
Disabling access port protection
Debugger registers
Debug side registers
RESET
ERASEALL
ERASEALLSTATUS
APPROTECT.DISABLE
SECUREAPPROTECT.DISABLE
ERASEPROTECT.STATUS
ERASEPROTECT.DISABLE
MAILBOX.TXDATA
MAILBOX.TXSTATUS
MAILBOX.RXDATA
MAILBOX.RXSTATUS
IDR
Registers
MAILBOX.RXDATA
MAILBOX.RXSTATUS
MAILBOX.TXDATA
MAILBOX.TXSTATUS
ERASEPROTECT.LOCK
ERASEPROTECT.DISABLE
APPROTECT.LOCK
APPROTECT.DISABLE
SECUREAPPROTECT.LOCK
SECUREAPPROTECT.DISABLE
STATUS
CTI - Cross Trigger Interface
Registers
CTICONTROL
CTIINTACK
CTIAPPSET
CTIAPPCLEAR
CTIAPPPULSE
CTIINEN[n]
CTIOUTEN[n]
CTITRIGINSTATUS
CTITRIGOUTSTATUS
CTICHINSTATUS
CTIGATE
DEVARCH
DEVID
DEVTYPE
PIDR4
PIDR5
PIDR6
PIDR7
PIDR0
PIDR1
PIDR2
PIDR3
CIDR0
CIDR1
CIDR2
CIDR3
TAD - Trace and debug control
Registers
CLOCKSTART
CLOCKSTOP
ENABLE
PSEL.TRACECLK
PSEL.TRACEDATA0
PSEL.TRACEDATA1
PSEL.TRACEDATA2
PSEL.TRACEDATA3
TRACEPORTSPEED (Retained)
Hardware and layout
Pin assignments
aQFN94 pin assignments
WLCSP pin assignments
Mechanical specifications
aQFN94 7 x 7 mm package
CLAA WLCSP package
CMAA WLCSP package
Reference circuitry
Circuit configuration no. 1 for QKAA aQFN94
Circuit configuration no. 2 for QKAA aQFN94
Circuit configuration no. 3 for QKAA aQFN94
Circuit configuration no. 4 for QKAA aQFN94
Circuit configuration no. 1 for CLAA WLCSP
Circuit configuration no. 2 for CLAA WLCSP
Circuit configuration no. 3 for CLAA WLCSP
Circuit configuration no. 4 for CLAA WLCSP
Circuit configuration no. 1 for CMAA WLCSP
Circuit configuration no. 2 for CMAA WLCSP
Circuit configuration no. 3 for CMAA WLCSP
Circuit configuration no. 4 for CMAA WLCSP
PCB layout example
PMIC support
Package thermal characteristics
Recommended operating conditions
WLCSP light sensitivity
Absolute maximum ratings
Ordering information
Device marking
Box labels
Order code
Code ranges and values
Product options
Legal notices

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