Cache information is divided into cache info content and cache data content.
Cache info content is organized in memory as shown in the following figure. Figure 2. Cache info content
The V field contains the bit that indicates if a cache entry is valid or not. All V
fields are cleared when invalidating the cache using register INVALIDATE, when disabling the cache using register ENABLE, or when changing
MODE from Ram to Cache. The MRU field indicates which way
was used most recently in the set. The MRU bit is updated on each fetch from the cache and is
used for the cache replacement policy. The Tag field is used to check if an entry in the cache
matches the address being fetched.
The following figure shows how the cache data content is organized in memory. Figure 3. Cache data content
Each set consists of two ways, each containing 128 bits of data. The 128-bit data is
available as 4x32-bit words in sequential order. When operating in Ram mode (MODE = Ram), the data is accessible as general purpose RAM.
The cache info and cache data content are memory mapped in the CACHEINFO and CACHEDATA
regions. These can be accessed in the CACHEINFO
registers and CACHEDATA registers
respectively.
