ICR

Address offset: 0xA08

Interrupt clear register. Writing a 1 bit into a field in this register will clear the corresponding bit in IRR.


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																								H	G	F	E	D	C	B	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	W	SRAM_TO_DIN_CLEAR										The RNG SRAM to DIN DMA done interrupt clear.
B	W	DOUT_TO_SRAM_CLEAR										The DOUT to RNG SRAM DMA done interrupt clear.
C	W	MEM_TO_DIN_CLEAR										The memory to DIN DMA done interrupt clear.
D	W	DOUT_TO_MEM_CLEAR										The DOUT to memory DMA done interrupt clear.
E	W	AHB_ERR_CLEAR										The AHB error interrupt clear.
F	W	PKA_CLEAR										The PKA end of operation interrupt clear.
G	W	RNG_CLEAR										The RNG interrupt clear. Register RNG_ISR in the RNG engine must be cleared before this interrupt can be cleared.
H	W	SYM_DMA_CLEAR										The symmetric engine DMA completed interrupt clear.