AES_HW_FLAGS

nRF5340 Product Specification

Address offset: 0x4C8

Hardware configuration of the AES engine. Reset value holds the supported features.

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID K J I H G F E D C B A
Reset 0x00001D0B 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 1 0 0 0 0 1 0 1 1
ID R/W Field Value ID Value Description
A

R

SUPPORT_256_192_KEY

If this flag is set, the engine support 192 bits and 256 bits key size.

B

R

AES_LARGE_RKEK

If this flag is set, the engine support AES_LARGE_RKEK.

C

R

DPA_CNTRMSR_EXIST

If this flag is set, the engine support DPA countermeasures.

D

R

CTR_EXIST

If this flag is set, the engine support AES CTR mode.

E

R

ONLY_ENCRYPT

If this flag is set, the engine only support encrypt operations.

F

R

USE_SBOX_TABLE

If this flag is set, the engine uses SBOX tables.

G

R

USE_5_SBOXES

If this flag is set, the engine uses 5 SBOX where each AES round takes 4 cycles.

H

R

AES_SUPPORT_PREV_IV

If this flag is set, the engine contains the PREV_IV register for faster AES XCBC MAC calculation.

I

R

AES_TUNNEL_EXIST

If this flag is set, the engine support tunneling operations.

J

R

SECOND_REGS_SET_EXIST

If this flag is set, the engine support a second register set for tunneling operations.

K

R

DFA_CNTRMSR_EXIST

If this flag is set, the engine support DFA countermeasures.