SPU also controls custom logic for an Arm TrustZone for Cortex®-M enabled CPU.
Custom logic is shown as the implementation defined attribution unit (IDAU) in figure Simplified view of SPU protection. Full support is provided for the following:
- Arm TrustZone for Cortex-M related instructions, like test target (TT) for reporting the security attributes of a region
- Non-secure callable (NSC) regions, to implement secure entry points from non-secure code
SPU provides the necessary registers to configure the security attributes for memory regions and peripherals. However, as a requirement to use SPU, the secure attribution unit (SAU) needs to be disabled and all memory set as non-secure in the Arm core. This will allow SPU to control the IDAU and set the security attribution of all addresses as originally intended.