Registers

Used by CPU to write data directly to the DIN buffer, which is then sent to the cryptographic engines for processing.

Status register for DIN DMA engine activity when accessing memory.

Data source address in memory.

The number of bytes to be read from memory. Writing to this register triggers the DMA operation.

Data source address in RNG SRAM.

The number of bytes to be read from RNG SRAM. Writing to this register triggers the DMA operation.

Status register for DIN DMA engine activity when accessing RNG SRAM.

Configure the endianness of DIN DMA transactions towards RNG SRAM.

Reset the DIN DMA engine.

Specifies the number of bytes the CPU will write to the DIN_BUFFER, ensuring the cryptographic engine processes the correct amount of data.

Indicates that the next CPU write to the DIN_BUFFER is the last in the sequence. This is needed only when the data size is NOT modulo 4 (e.g. HASH padding).

Register indicating if DIN FIFO is empty and if more data can be accepted.

Reset the DIN FIFO, effectively clearing the FIFO for new data.