PIN_CNF[n]

nRF5340 Product Specification

Address offset: 0x200 + (n × 0x4)

Configuration of GPIO pins

This register is retained.

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID F F F E E D D D D C C B A
Reset 0x00000002 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
ID R/W Field Value ID Value Description
A

RW

DIR

Pin direction. Same physical register as DIR register

Input

0

Configure pin as an input pin

Output

1

Configure pin as an output pin

B

RW

INPUT

Connect or disconnect input buffer

Connect

0

Connect input buffer

Disconnect

1

Disconnect input buffer

C

RW

PULL

Pull configuration

Disabled

0

No pull

Pulldown

1

Pull down on pin

Pullup

3

Pull up on pin

D

RW

DRIVE

Drive configuration

Some pins may not support every drive configuration.

S0S1

0

Standard '0', standard '1'

H0S1

1

High drive '0', standard '1'

S0H1

2

Standard '0', high drive '1'

H0H1

3

High drive '0', high 'drive '1''

D0S1

4

Disconnect '0', standard '1' (normally used for wired-or connections)

D0H1

5

Disconnect '0', high drive '1' (normally used for wired-or connections)

S0D1

6

Standard '0', disconnect '1' (normally used for wired-and connections)

H0D1

7

High drive '0', disconnect '1' (normally used for wired-and connections)

E0E1

11

Extra high drive '0', extra high drive '1'

E

RW

SENSE

Pin sensing mechanism

Disabled

0

Disabled

High

2

Sense for high level

Low

3

Sense for low level

F

RW

MCUSEL

Select which MCU/Subsystem controls this pin

Note: this field is only accessible from secure code.

AppMCU

0x0

Application MCU

NetworkMCU

0x1

Network MCU

Peripheral

0x3

Peripheral with dedicated pins

TND

0x7

Trace and Debug Subsystem