Registers

Register for mapping the virtual register R[n] to a physical address in the PKA SRAM.

Operation code to be executed by the PKA engine.

Writing to this register triggers the PKA operation.

This register defines the N, Np, T0, and T1 virtual register index.

This register holds the status for the PKA pipeline.

Reset the PKA engine.

This register holds the operands bit size.

Status register indicating if the PKA pipeline is ready to receive a new OPCODE.

Status register indicating if the PKA operation has been completed.

PKA engine HW version. Reset value holds the version.

Start address in PKA SRAM for subsequent write transactions.

Write data to PKA SRAM. Writing to this register triggers a DMA transaction writing data into PKA SRAM. The DMA address offset is automatically incremented during write.

Read data from PKA SRAM. Reading from this register triggers a DMA transaction read data from PKA SRAM. The DMA address offset is automatically incremented during read.

Register for clearing PKA SRAM write buffer.

Start address in PKA SRAM for subsequent read transactions.