Address offset: 0x800 + (n × 0x4)
List capabilities and access permissions for the peripheral with ID n
| Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
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| ID | F | E | D | C | B | B | A | A | |||||||||||||||||||||||||||
| Reset 0x00000012 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | |||
| ID | R/W | Field | Value ID | Value | Description | ||||||||||||||||||||||||||||||
| A |
R |
SECUREMAPPING |
Define configuration capabilities for Arm TrustZone Cortex-M secure attribute |
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NonSecure |
0 |
This peripheral is always accessible as a non-secure peripheral |
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Secure |
1 |
This peripheral is always accessible as a secure peripheral |
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|
UserSelectable |
2 |
Non-secure or secure attribute for this peripheral is defined by the PERIPHID[n].PERM register |
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Split |
3 |
This peripheral implements the split security mechanism. Non-secure or secure attribute for this peripheral is defined by the PERIPHID[n].PERM register. |
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| B |
R |
DMA |
Indicates if the peripheral has DMA capabilities and if DMA transfer can be assigned to a different security attribute than the peripheral itself |
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NoDMA |
0 |
Peripheral has no DMA capability |
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|
NoSeparateAttribute |
1 |
Peripheral has DMA and DMA transfers always have the same security attribute as assigned to the peripheral |
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|
SeparateAttribute |
2 |
Peripheral has DMA and DMA transfers can have a different security attribute than the one assigned to the peripheral |
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| C |
RW |
SECATTR |
Peripheral security mapping This bit has effect only if PERIPHID[n].PERM.SECUREMAPPING reads as UserSelectable or Split |
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|
Secure |
1 |
Peripheral is mapped in secure peripheral address space |
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|
NonSecure |
0 |
If SECUREMAPPING == UserSelectable: Peripheral is mapped in non-secure peripheral address space. If SECUREMAPPING == Split: Peripheral is mapped in non-secure and secure peripheral address space. |
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| D |
RW |
DMASEC |
Security attribution for the DMA transfer This bit has effect only if PERIPHID[n].PERM.SECATTR is set to secure |
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|
Secure |
1 |
DMA transfers initiated by this peripheral have the secure attribute set |
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NonSecure |
0 |
DMA transfers initiated by this peripheral have the non-secure attribute set |
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| E |
RW |
LOCK |
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|
Unlocked |
0 |
This register can be updated |
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Locked |
1 |
The content of this register can't be changed until the next reset |
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| F |
R |
PRESENT |
Indicate if a peripheral is present with ID n |
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NotPresent |
0 |
Peripheral is not present |
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|
IsPresent |
1 |
Peripheral is present |
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