Power and clock management of the CRYPTOCELL subsystem is handled automatically in hardware, as long as the neccessary conditions are fulfilled by software.
Clock gating
CRYPTOCELL implements separate clock domains for each cryptographic engine. Internal clock gating control is handled through the MISC interface, as well as register RNG_CLK. The registers of a cryptographic engine are only accessible when its clock is enabled.
Power gating
CRYPTOCELL must be disabled to ensure lowest possible power consumption when the subsystem is not needed.
The CRYPTOCELL subsystem power is controlled through register ENABLE. Even though external clock input is gated away automatically
by hardware, the CRYPTOCELL subsystem power will still be enabled. To initiate a full
power-down sequence software must perform the following steps:
- Make sure there are no pending tasks
- Verify that CRYPTOCELL subsystem is idle using register HOST_CC_IS_IDLE.
- Clear all pending interrupts in register RNG_ICR and register ICR.
- Request power-down by writing to register HOST_POWERDOWN.
- Disable CRYPTOCELL subsystem using register ENABLE.
If the power-down request in step 4 has been issued, the CRYPTOCELL subsystem must be disabled, as outlined in step 5.