Address offset: 0x600
Interface configuration.
| Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
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| ID | D | D | D | D | C | B | A | A | A | A | A | A | A | A | |||||||||||||||||||||
| Reset 0x00040480 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||
| ID | R/W | Field | Value ID | Value | Description | ||||||||||||||||||||||||||||||
| A |
RW |
SCKDELAY |
[0..255] |
Minimum amount of time that the CSN pin must stay high before it can go low again. Value is specified in number of 32 MHz periods (31.25 ns). |
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| B |
RW |
DPMEN |
Enter/exit deep power-down mode (DPM) for external flash memory. |
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|
Exit |
0 |
Exit DPM. |
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|
Enter |
1 |
Enter DPM. |
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| C |
RW |
SPIMODE |
Select SPI mode. |
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|
MODE0 |
0 |
Mode 0: Data are captured on the clock rising edge and data is output on a falling edge. Base level of clock is 0 (CPOL=0, CPHA=0). |
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|
MODE3 |
1 |
Mode 3: Data are captured on the clock rising edge and data is output on a falling edge. Base level of clock is 1 (CPOL=1, CPHA=1). |
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| D |
RW |
SCKFREQ |
[0..15] |
SCK frequency is derived from PCLK192M with SCK frequency = PCLK192M / (2*(SCKFREQ + 1)). |
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