Cryptographic flow

    
    uint8_t buf_dst[16] = { 0 };
    uint8_t buf_src[16] = { 0x81, 0x02, 0xF2, 0x40, 0xD5, 0xB9, 0x44, 0x59,
                            0xA2, 0xEB, 0x6F, 0xF2, 0x49, 0xF5, 0xEB, 0x94 };
   
    /* Enable CRYPTOCELL subsystem */
    NRF_CRYPTOCELL->ENABLE =  CRYPTOCELL_ENABLE_ENABLE_Enabled;

    /* Enable engine and DMA clock */
    NRF_CC_MISC->AES_CLK = CC_MISC_AES_CLK_ENABLE_Enable;
    NRF_CC_MISC->DMA_CLK = CC_MISC_DMA_CLK_ENABLE_Enable;

    /* Wait until crypto engine is Idle  */
    while (NRF_CC_CTL->CRYPTO_BUSY == CC_CTL_CRYPTO_BUSY_STATUS_Busy) { }

    /* Configure AES as cryptographic flow */
    NRF_CC_CTL->CRYPTO_CTL = CC_CTL_CRYPTO_CTL_MODE_AESActive;

    /* Configure AES engine control for decryption using ECB mode (default) */
    NRF_CC_AES->AES_CONTROL = CC_AES_AES_CONTROL_DEC_KEY0_Decrypt;

    /* Load the AES key value into the engine */
    NRF_CC_AES->AES_KEY_0[0] = 0x51515151;
    NRF_CC_AES->AES_KEY_0[1] = 0x52525252;
    NRF_CC_AES->AES_KEY_0[2] = 0x53535353;
    NRF_CC_AES->AES_KEY_0[3] = 0x54545454;

    /* Configure default init vector */
    NRF_CC_AES->AES_IV_0[0] = 0x0;
    NRF_CC_AES->AES_IV_0[1] = 0x0;
    NRF_CC_AES->AES_IV_0[2] = 0x0;
    NRF_CC_AES->AES_IV_0[3] = 0x0;

    /* Configure DMA output destination address */
    NRF_CC_DOUT->DST_MEM_ADDR = (uint32_t) buf_dst;
    NRF_CC_DOUT->DST_MEM_SIZE = (uint32_t) sizeof(buf_dst);

    /* Configure DMA input source address to start the cryptographic operation */
    NRF_CC_DIN->SRC_MEM_ADDR = (uint32_t) buf_src;
    NRF_CC_DIN->SRC_MEM_SIZE = (uint32_t) sizeof(buf_src);

    /* Wait on DOUT DMA interrupt */
    while(!(NRF_CC_HOST_RGF->IRR & CC_HOST_RGF_IRR_DOUT_TO_MEM_INT_Msk)) {}