Instances
| Instance | Domain | Base address | TrustZone | Split access | Description | ||
|---|---|---|---|---|---|---|---|
| Map | Att | DMA | |||||
| CC_HASH | APPLICATION | 0x50845000 | HF | S | NSA | No |
CRYPTOCELL HASH engine |
Register overview
| Register | Offset | TZ | Description |
|---|---|---|---|
| HASH_H[n] | 0x640 |
HASH_H value registers. The initial HASH_H[0] register holds the least significant bits [31:0] of the value. |
|
| HASH_PAD_AUTO | 0x684 |
Configure the HASH engine to automatically pad data at the end of the DMA transfer to complete the digest operation. |
|
| HASH_XOR_DIN | 0x688 |
Perform an XOR operation of the DIN DMA engine input data being fed into the HASH engine. Set this register to '0' if XOR is not required. |
|
| HASH_INIT_STATE | 0x694 |
Configure HASH engine initial state registers. |
|
| HASH_SELECT | 0x6A4 |
Select HASH or GHASH engine as the digest engine to use. |
|
| HASH_CONTROL | 0x7C0 |
Control the HASH engine behavior. |
|
| HASH_PAD | 0x7C4 |
Enable the hardware padding feature of the HASH engine. |
|
| HASH_PAD_FORCE | 0x7C8 |
Force the hardware padding operation to trigger if the input data length is zero bytes. |
|
| HASH_CUR_LEN_0 | 0x7CC |
Bits [31:0] of the number of bytes that have been digested so far. |
|
| HASH_CUR_LEN_1 | 0x7D0 |
Bits [63:32] of the number of bytes that have been digested so far. |
|
| HASH_HW_FLAGS | 0x7DC |
Hardware configuration of the HASH engine. Reset value holds the supported features. |
|
| HASH_SW_RESET | 0x7E4 |
Reset the HASH engine. |
|
| HASH_ENDIANNESS | 0x7E8 |
Configure the endianness of HASH data and padding generation. |