Registers

Interrupt mask register. Each bit of this register holds the mask of a single interrupt source.

Interrupt status register. Each bit of this register holds the interrupt status of a single interrupt source. If corresponding RNG_IMR bit is unmasked, an interrupt is generated.

Interrupt clear register. Writing a 1 bit into a field in this register will clear the corresponding bit in RNG_ISR.

TRNG ring oscillator length configuration

This register indicates if TRNG entropy collection is valid.

The entropy holding registers (EHR) hold 192-bits random data collected by the TRNG.

The initial EHR_DATA[0] register holds the least significant bits [31:0] of the random data value.

This register controls the ring oscillator circuit used as a noise source.

Sample count defining the number of CPU clock cycles between two consecutive noise source samples.

Statistics counter for autocorrelation test activations. Statistics collection is stopped if one of the counters reach its limit of all ones.

Debug register for the TRNG. This register is used to bypass TRNG tests in hardware.

Reset the RNG engine.

Status register for RNG engine activity.

Reset the TRNG, including internal counter of collected bits and registers EHR_DATA and TRNG_VALID.

Hardware configuration of RNG engine. Reset value holds the supported features.

Control clock for the RNG engine.

Writing to this register enables the RNG DMA engine.

This register defines which ring oscillator length configuration should be used when using the RNG DMA engine.

This register defines the start address in TRNG SRAM for the TRNG data to be collected by the RNG DMA engine.

This register defines the number of 192-bits samples that the RNG DMA engine collects per run.

This register defines the maximum number of CPU clock cycles per TRNG collection of 192-bits samples. If the number of cycles for a collection exceeds this threshold the WATCHDOG interrupt is triggered.

Status register for RNG DMA engine activity.