Assigning pins between cores, peripherals, or subsystems

GPIO pins of the system can be allocated among the cores, peripherals with dedicated pins, or subsystems such as trace and debug.

The pins of the system are listed in Pin assignments.

By default, all pins are assigned to the application core. The application core's MCUSEL bitfield in register PIN_CNF[n] (n=0..31) (Retained) controls the allocation of the pins into cores, peripherals and the TaD subsystem.

The pin's state, being either an output, input, or analog, can only be controlled and observed by the core for which the pin was allocated. Reading a pin that is not allocated to the current core will return zero, and writes will be ignored. If a pin is allocated to a subsystem that cannot access it, the pin stays under control of the application core's GPIO peripheral.

The GPIO peripheral of any core has its own set of registers that can be read and written independently, but they only affect a pin when it has been allocated to this core. Reading the GPIO peripheral registers of one core does not reveal the register contents of a different core.

The following figure illustrates how to assign a pin to a core, to a peripheral that has dedicated pins, or a subsystem such as trace and debug.

Also note that when a pin p is not assigned to the application core, the application core's GPIO LATCH register, PIN_CNF[p].MCUSEL bitfield, and PIN_CNF[p].SENSE bitfield is prevented. For these, any write operations are ignored, and any read operation will return 0.