| Symbol | Description | Min. | Typ. | Max. | Units |
|---|---|---|---|---|---|
| tS_SDIN |
SDIN setup time before SCK rising |
20 | ns | ||
| tH_SDIN |
SDIN hold time after SCK rising |
15 | ns | ||
| tS_SDOUT |
SDOUT setup time after SCK falling |
50 | ns | ||
| tH_SDOUT |
SDOUT hold time after SCK falling |
13 | ns | ||
| tSCK_LRCK |
SCLK falling to LRCK edge |
-5 | 0 | 5 | ns |
| fMCK |
MCK frequency |
12288 | kHz | ||
| fLRCK |
LRCK frequency |
96 | kHz | ||
| fSCK |
SCK frequency |
8000 | kHz | ||
| DCCK |
Clock duty cycle (MCK, LRCK, SCK) |
45 | 55 | % |