CH[n].CONFIG

Address offset: 0x518 + (n × 0x10)

Input configuration for CH[n]


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID											G				F		E	E	E				D		C	C	C			B	B			A	A
Reset 0x00020000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	RESP										Positive channel resistor control
			Bypass	0								Bypass resistor ladder
			Pulldown	1								Pull-down to GND
			Pullup	2								Pull-up to VDD
			VDD1_2	3								Set input at VDD/2
B	RW	RESN										Negative channel resistor control
			Bypass	0								Bypass resistor ladder
			Pulldown	1								Pull-down to GND
			Pullup	2								Pull-up to VDD
			VDD1_2	3								Set input at VDD/2
C	RW	GAIN										Gain control
			Gain1_6	0								1/6
			Gain1_5	1								1/5
			Gain1_4	2								1/4
			Gain1_3	3								1/3
			Gain1_2	4								1/2
			Gain1	5								1
			Gain2	6								2
			Gain4	7								4
D-	RW	REFSEL										Reference control
			Internal	0								Internal reference (0.6 V)
			VDD1_4	1								VDD/4 as reference
E	RW	TACQ										Acquisition time, the time the ADC uses to sample the input voltage
			3us	0								3 µs
			5us	1								5 µs
			10us	2								10 µs
			15us	3								15 µs
			20us	4								20 µs
			40us	5								40 µs
F	RW	MODE										Enable differential mode
			SE	0								Single-ended, PSELN will be ignored, negative input to ADC shorted to GND
			Diff	1								Differential
G	RW	BURST										Enable burst mode
			Disabled	0								Burst mode is disabled (normal operation)
			Enabled	1								Burst mode is enabled. SAADC takes 2^OVERSAMPLE number of samples as fast as it can, and sends the average to Data RAM.