Network core reset behavior

Network core reset behavior depends on the reset source.

In System OFF mode, or when the network core is held in Force-OFF, the watchdog timer is not running and there is no CPU lockup possible. RAM may be fully or partially retained, depending on RAM retention settings in VMC — Volatile memory controller.

If the device is in Debug Interface mode, the debug components will not be reset. Additionally, CPU lockup will not generate a reset. See Debug and trace for more information about the different debug components in the system.

Any reset in the application core will cause a network core force off, triggering the network FORCEOFF reset source in the following table. For more information, see Network Force-OFF.

Table 3. Network core reset target sourcesAn 'x' in the table means that the specific module is reset. Pin reset, brownout reset, and power-on reset are system level reset sources with the network core and application core having the same behavior, see Application core reset behavior.
Reset source	Reset target
Reset source	CPU	RAM	WDT	RESETREAS
CPU lockup	x
Soft reset	x
Network FORCEOFF	x	x^³	x
Application Watchdog timer reset	x	x	x
Local Watchdog timer reset	x	x	x

Note: RAM is never reset, but its content may be corrupted depending on the reset source.

Some retained registers may have a different reset behavior, as shown in following table.

Table 4. Network core reset behavior for retained registersAn 'x' in the table means that the specific module is reset. Pin reset, brownout reset, and power-on reset are system level reset sources with the network core and application core having the same behavior, see Application core reset behavior.
Reset source	Reset target
Reset source	Regular peripheral registers	GPIO	POWER.GPREGRET
CPU lockup	x	x ^⁴
Soft reset	x	x ^⁴
Network FORCEOFF	x
Application Watchdog timer reset	x	x
Local Watchdog timer reset	x	x

³ Depending on RAM retention settings.

⁴ MCUSEL settings are kept.