Instances
| Instance | Domain | Base address | TrustZone | Split access | Description | ||
|---|---|---|---|---|---|---|---|
| Map | Att | DMA | |||||
| CACHE | APPLICATION | 0x50001000 | HF | S | NA | No |
Cache |
Register overview
| Register | Offset | TZ | Description |
|---|---|---|---|
| PROFILING[n].IHIT | 0x400 |
Instruction fetch cache hit counter for cache region n, where n=0 means Flash and n=1 means XIP. |
|
| PROFILING[n].IMISS | 0x404 |
Instruction fetch cache miss counter for cache region n, where n=0 means Flash and n=1 means XIP. |
|
| PROFILING[n].DHIT | 0x408 |
Data fetch cache hit counter for cache region n, where n=0 means Flash and n=1 means XIP. |
|
| PROFILING[n].DMISS | 0x40C |
Data fetch cache miss counter for cache region n, where n=0 means Flash and n=1 means XIP. |
|
| ENABLE | 0x500 |
Enable cache. |
|
| INVALIDATE | 0x504 |
Invalidate the cache. |
|
| ERASE | 0x508 |
Erase the cache. |
|
| PROFILINGENABLE | 0x50C |
Enable the profiling counters. |
|
| PROFILINGCLEAR | 0x510 |
Clear the profiling counters. |
|
| MODE | 0x514 |
Cache mode. Switching from Cache to Ram mode causes the RAM to be cleared. Switching from RAM to Cache mode causes the cache to be invalidated. |
|
| DEBUGLOCK | 0x518 |
Lock debug mode. |
|
| ERASESTATUS | 0x51C |
Cache erase status. |
|
| WRITELOCK | 0x520 |
Lock cache updates. Prevents updating of cache content on cache misses, but will continue to lookup instruction/data fetches in content already present in the cache. Ignored in RAM mode. |