| Symbol | Description | Min. | Typ. | Max. | Units |
|---|---|---|---|---|---|
| fPDM,CLK,64 |
PDM clock speed. PDMCLKCTRL = Default (Setting needed for 16 MHz sample frequency @ RATIO = Ratio64) |
1.032 | MHz | ||
| fPDM,CLK,80 |
PDM clock speed. PDMCLKCTRL = 1280K (Setting needed for 16 MHz sample frequency @ RATIO = Ratio80) |
1.280 | MHz | ||
| tPDM,JITTER |
Jitter in PDM clock output |
20 | ns | ||
| TdPDM,CLK |
PDM clock duty cycle |
40 | 50 | 60 | % |
| tPDM,DATA |
Decimation filter delay |
5 | ms | ||
| tPDM,cv |
Allowed clock edge to data valid |
125 | ns | ||
| tPDM,ci |
Allowed (other) clock edge to data invalid |
0 | ns | ||
| tPDM,s |
Data setup time at fPDM,CLK = 1.024 MHz or 1.280 MHz |
65 | ns | ||
| tPDM,h |
Data hold time at fPDM,CLK = 1.024 MHz or 1.280 MHz |
0 | ns | ||
| GPDM,default |
Default (reset) absolute gain of the PDM module |
3.2 | dB |