Instances
| Instance | Domain | Base address | TrustZone | Split access | Description | ||
|---|---|---|---|---|---|---|---|
| Map | Att | DMA | |||||
| TAD | APPLICATION | 0xE0080000 | HF | S | NA | No |
Trace and debug control |
Register overview
| Register | Offset | TZ | Description |
|---|---|---|---|
| CLOCKSTART | 0x004 |
Start all trace and debug clocks. |
|
| CLOCKSTOP | 0x008 |
Stop all trace and debug clocks. |
|
| ENABLE | 0x500 |
Enable debug domain and aquire selected GPIOs |
|
| PSEL.TRACECLK | 0x504 |
Pin configuration for TRACECLK |
|
| PSEL.TRACEDATA0 | 0x508 |
Pin configuration for TRACEDATA[0] |
|
| PSEL.TRACEDATA1 | 0x50C |
Pin configuration for TRACEDATA[1] |
|
| PSEL.TRACEDATA2 | 0x510 |
Pin configuration for TRACEDATA[2] |
|
| PSEL.TRACEDATA3 | 0x514 |
Pin configuration for TRACEDATA[3] |
|
| TRACEPORTSPEED | 0x518 |
Clocking options for the Trace Port debug interface Reset behavior is the same as debug components This register is retained. |