PKA SRAM

The 6 kB PKA SRAM memory connected to the PKA engine is used exclusively by the engine during cryptographic operations. All access to this memory is blocked while the PKA engine is processing.

The PKA SRAM memory is not directly mapped to the device memory map. Instead, any read or write operation to this memory region must be done using the PKA engine.

Writing data to the PKA SRAM involves the following steps:

Set the Address Offset: Specify the starting byte address for writing by setting register PKA_SRAM_WADDR. An offset value of 0x0 points to the first 32-bits word in the PKA SRAM memory. An offset value of 0x10 points to the fourth 32-bits word in the PKA SRAM memory.
Write Data: After setting the address offset, data is written to register PKA_SRAM_WDATA. The address will automatically increment after each write, allowing writes to the next word without needing to set the offset again.

Reading data from the PKA SRAM involves the following steps:

Set the Read Address: Specify the starting byte address for reading by setting register PKA_SRAM_RADDR
Read Data: Retrieve the data from register PKA_SRAM_RDATA. Similar to the write address, the read address will auto-increment with each read, setting it to the next word.

Note: Before switching from writing to reading operations (or vice versa), the PKA SRAM write buffer must be cleared. This is done using register PKA_SRAM_WCLEAR. Clearing the buffer ensures that the next operation starts cleanly without any leftover data from the previous operation.