Registers

Flush RX FIFO into RX buffer

Starts operation using easyDMA to load the values. See peripheral description for operation using easyDMA.

Stops operation using easyDMA. This does not trigger an END event.

Enables the MATCH[n] event by setting the ENABLE[n] bit in the CONFIG register.

Disables the MATCH[n] event by clearing the ENABLE[n] bit in the CONFIG register.

Starts operation using easyDMA to load the values. See peripheral description for operation using easyDMA.

Stops operation using easyDMA. This does not trigger an END event.

Subscribe configuration for task FLUSHRX

Subscribe configuration for task START

Subscribe configuration for task STOP

Subscribe configuration for task ENABLEMATCH[n]

Subscribe configuration for task DISABLEMATCH[n]

Subscribe configuration for task START

Subscribe configuration for task STOP

CTS is activated (set low). Clear To Send.

CTS is deactivated (set high). Not Clear To Send.

Data sent from TXD

Data received in RXD (but potentially not yet transferred to Data RAM)

Error detected

Receiver timeout

Transmitter stopped

Generated after EasyDMA has completed its operation.

Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them to be written to prepare for the next sequence.

An error occured during the bus transfer.

Pattern match is detected on the DMA data bus.

Generated after EasyDMA has completed its operation.

Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them to be written to prepare for the next sequence.

An error occured during the bus transfer.

Timed out due to bus being idle while receiving data.

Publish configuration for event CTS

Publish configuration for event NCTS

Publish configuration for event TXDRDY

Publish configuration for event RXDRDY

Publish configuration for event ERROR

Publish configuration for event RXTO

Publish configuration for event TXSTOPPED

Publish configuration for event END

Publish configuration for event READY

Publish configuration for event BUSERROR

Publish configuration for event MATCH[n]

Publish configuration for event END

Publish configuration for event READY

Publish configuration for event BUSERROR

Publish configuration for event FRAMETIMEOUT

Shortcuts between local events and tasks

Enable or disable interrupt

Enable interrupt

Disable interrupt

Error source

Enable UART

Baud rate. Accuracy depends on the HFCLK source selected.

Configuration of parity, hardware flow control, framesize, and packet timeout.

Set the address of the UARTE for RX when used in 9 bit data frame mode.

Set the number of UARTE bits to count before triggering packet timeout.

Pin select for TXD signal

Pin select for CTS signal

Pin select for RXD signal

Pin select for RTS signal

RAM buffer start address

Maximum number of bytes in channel buffer

Number of bytes transferred in the last transaction, updated after the END event.

Also updated after each MATCH event.

Terminate the transaction if a BUSERROR event is detected.

Address of transaction that generated the last BUSERROR event.

Configure individual match events

The data to look for - any match will trigger the MATCH[n] event, if enabled.

RAM buffer start address

Maximum number of bytes in channel buffer

Number of bytes transferred in the last transaction, updated after the END event.

Also updated after each MATCH event.

Terminate the transaction if a BUSERROR event is detected.

Address of transaction that generated the last BUSERROR event.